📄 mypaomadeng.fit.rpt
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; Weak Pull-Up Resistor ; Off ; Off ;
; Enable Bus-Hold Circuitry ; Off ; Off ;
; Auto Global Memory Control Signals ; Off ; Off ;
; Auto Packed Registers -- Stratix II/II GX/III Cyclone II/III Arria GX ; Auto ; Auto ;
; Auto Delay Chains ; On ; On ;
; Auto Merge PLLs ; On ; On ;
; Ignore PLL Mode When Merging PLLs ; Off ; Off ;
; Perform Physical Synthesis for Combinational Logic for Fitting ; Off ; Off ;
; Perform Physical Synthesis for Combinational Logic for Performance ; Off ; Off ;
; Perform Register Duplication for Performance ; Off ; Off ;
; Perform Logic to Memory Mapping for Fitting ; Off ; Off ;
; Perform Register Retiming for Performance ; Off ; Off ;
; Perform Asynchronous Signal Pipelining ; Off ; Off ;
; Fitter Effort ; Auto Fit ; Auto Fit ;
; Physical Synthesis Effort Level ; Normal ; Normal ;
; Auto Global Clock ; On ; On ;
; Auto Global Register Control Signals ; On ; On ;
; Stop After Congestion Map Generation ; Off ; Off ;
; Save Intermediate Fitting Results ; Off ; Off ;
+-----------------------------------------------------------------------+--------------------------------+--------------------------------+
+--------------+
; Pin-Out File ;
+--------------+
The pin-out file can be found in E:/Altera/exercise/mypaomadeng/mypaomadeng.pin.
+---------------------------------------------------------------------------+
; Fitter Resource Usage Summary ;
+---------------------------------------------+-----------------------------+
; Resource ; Usage ;
+---------------------------------------------+-----------------------------+
; Total logic elements ; 62 / 4,608 ( 1 % ) ;
; -- Combinational with no register ; 20 ;
; -- Register only ; 0 ;
; -- Combinational with a register ; 42 ;
; ; ;
; Logic element usage by number of LUT inputs ; ;
; -- 4 input functions ; 23 ;
; -- 3 input functions ; 4 ;
; -- <=2 input functions ; 35 ;
; -- Register only ; 0 ;
; ; ;
; Logic elements by mode ; ;
; -- normal mode ; 34 ;
; -- arithmetic mode ; 28 ;
; ; ;
; Total registers* ; 42 / 5,010 ( < 1 % ) ;
; -- Dedicated logic registers ; 42 / 4,608 ( < 1 % ) ;
; -- I/O registers ; 0 / 402 ( 0 % ) ;
; ; ;
; Total LABs: partially or completely used ; 5 / 288 ( 2 % ) ;
; User inserted logic elements ; 0 ;
; Virtual pins ; 0 ;
; I/O pins ; 6 / 142 ( 4 % ) ;
; -- Clock pins ; 1 / 4 ( 25 % ) ;
; Global signals ; 2 ;
; M4Ks ; 0 / 26 ( 0 % ) ;
; Total memory bits ; 0 / 119,808 ( 0 % ) ;
; Total RAM block bits ; 0 / 119,808 ( 0 % ) ;
; Embedded Multiplier 9-bit elements ; 0 / 26 ( 0 % ) ;
; PLLs ; 0 / 2 ( 0 % ) ;
; Global clocks ; 2 / 8 ( 25 % ) ;
; Average interconnect usage ; 0% ;
; Peak interconnect usage ; 0% ;
; Maximum fan-out node ; int_div:inst3|LessThan0~661 ;
; Maximum fan-out ; 29 ;
; Highest non-global fan-out signal ; int_div:inst3|LessThan0~661 ;
; Highest non-global fan-out ; 29 ;
; Total fan-out ; 303 ;
; Average fan-out ; 2.63 ;
+---------------------------------------------+-----------------------------+
* Register count does not include registers inside RAM blocks or DSP blocks.
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Input Pins ;
+-------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+
; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Power Up High ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination ; Location assigned by ;
+-------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+
; clk ; 23 ; 1 ; 0 ; 6 ; 0 ; 2 ; 0 ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ;
; reset ; 56 ; 4 ; 1 ; 0 ; 2 ; 9 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ;
+-------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Output Pins ;
+--------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+----------------------+------+
; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Output Register ; Output Enable Register ; Power Up High ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination ; Location assigned by ; Load ;
+--------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+----------------------+------+
; led[0] ; 6 ; 1 ; 0 ; 12 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
; led[1] ; 5 ; 1 ; 0 ; 13 ; 4 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
; led[2] ; 3 ; 1 ; 0 ; 13 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
; led[3] ; 4 ; 1 ; 0 ; 13 ; 3 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+--------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+----------------------+------+
+-----------------------------------------------------------+
; I/O Bank Usage ;
+----------+-----------------+---------------+--------------+
; I/O Bank ; Usage ; VCCIO Voltage ; VREF Voltage ;
+----------+-----------------+---------------+--------------+
; 1 ; 7 / 34 ( 21 % ) ; 3.3V ; -- ;
; 2 ; 0 / 35 ( 0 % ) ; 3.3V ; -- ;
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