myjiaotongdeng.map.rpt

本例实现交通灯的控制

;                                             ;                        ;
; Total combinational functions               ; 100                    ;
; Logic element usage by number of LUT inputs ;                        ;
;     -- 4 input functions                    ; 47                     ;
;     -- 3 input functions                    ; 20                     ;
;     -- <=2 input functions                  ; 33                     ;
;                                             ;                        ;
; Logic elements by mode                      ;                        ;
;     -- normal mode                          ; 79                     ;
;     -- arithmetic mode                      ; 21                     ;
;                                             ;                        ;
; Total registers                             ; 42                     ;
;     -- Dedicated logic registers            ; 42                     ;
;     -- I/O registers                        ; 0                      ;
;                                             ;                        ;
; I/O pins                                    ; 15                     ;
; Maximum fan-out node                        ; jiao_tong:inst1|clk1hz ;
; Maximum fan-out                             ; 24                     ;
; Total fan-out                               ; 422                    ;
; Average fan-out                             ; 2.69                   ;
+---------------------------------------------+------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                     ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------------------+--------------+
; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name             ; Library Name ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------------------+--------------+
; |myjiaotongdeng            ; 100 (0)           ; 42 (0)       ; 0           ; 0            ; 0       ; 0         ; 15   ; 0            ; |myjiaotongdeng                 ; work         ;
;    |jiao_tong:inst1|       ; 100 (100)         ; 42 (42)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |myjiaotongdeng|jiao_tong:inst1 ; work         ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


Encoding Type:  One-Hot
+-----------------------------------------------------+
; State Machine - |myjiaotongdeng|jiao_tong:inst1|stx ;
+---------+---------+---------+---------+-------------+
; Name    ; stx.st4 ; stx.st3 ; stx.st2 ; stx.st1     ;
+---------+---------+---------+---------+-------------+
; stx.st1 ; 0       ; 0       ; 0       ; 0           ;
; stx.st2 ; 0       ; 0       ; 1       ; 1           ;
; stx.st3 ; 0       ; 1       ; 0       ; 1           ;
; stx.st4 ; 1       ; 0       ; 0       ; 1           ;
+---------+---------+---------+---------+-------------+


+--------------------------------------------------------------------------------+
; Registers Removed During Synthesis                                             ;
+---------------------------------------+----------------------------------------+
; Register name                         ; Reason for Removal                     ;
+---------------------------------------+----------------------------------------+
; jiao_tong:inst1|g2                    ; Merged with jiao_tong:inst1|r2         ;
; jiao_tong:inst1|counter[0]            ; Merged with jiao_tong:inst1|cnt[0]     ;
; jiao_tong:inst1|cnt[1]                ; Stuck at GND due to stuck port data_in ;
; Total Number of Removed Registers = 3 ;                                        ;
+---------------------------------------+----------------------------------------+


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 42    ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 0     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 14    ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                                           ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+--------------------------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output                 ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+--------------------------------------------+
; 6:1                ; 2 bits    ; 8 LEs         ; 2 LEs                ; 6 LEs                  ; Yes        ; |myjiaotongdeng|jiao_tong:inst1|g2         ;
; 9:1                ; 3 bits    ; 18 LEs        ; 6 LEs                ; 12 LEs                 ; Yes        ; |myjiaotongdeng|jiao_tong:inst1|qh[3]      ;
; 9:1                ; 4 bits    ; 24 LEs        ; 16 LEs               ; 8 LEs                  ; Yes        ; |myjiaotongdeng|jiao_tong:inst1|q1[3]      ;
; 12:1               ; 2 bits    ; 16 LEs        ; 4 LEs                ; 12 LEs                 ; No         ; |myjiaotongdeng|jiao_tong:inst1|Selector17 ;
; 12:1               ; 2 bits    ; 16 LEs        ; 4 LEs                ; 12 LEs                 ; No         ; |myjiaotongdeng|jiao_tong:inst1|Selector18 ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+--------------------------------------------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 7.2 Build 175 11/20/2007 Service Pack 1 SJ Full Version
    Info: Processing started: Mon May 26 14:03:31 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off myjiaotongdeng -c myjiaotongdeng
Info: Found 1 design units, including 1 entities, in source file myjiaotongdeng.bdf
    Info: Found entity 1: myjiaotongdeng
Info: Found 2 design units, including 1 entities, in source file jiao_tong.vhd
    Info: Found design unit 1: jiao_tong-one
    Info: Found entity 1: jiao_tong
Info: Elaborating entity "myjiaotongdeng" for the top level hierarchy
Info: Elaborating entity "jiao_tong" for hierarchy "jiao_tong:inst1"
Warning (10631): VHDL Process Statement warning at jiao_tong.vhd(192): inferring latch(es) for signal or variable "data", which holds its previous value in one or more paths through the process
Warning (10631): VHDL Process Statement warning at jiao_tong.vhd(192): inferring latch(es) for signal or variable "scan", which holds its previous value in one or more paths through the process
Info (10041): Inferred latch for "scan[0]" at jiao_tong.vhd(192)
Info (10041): Inferred latch for "scan[1]" at jiao_tong.vhd(192)
Info (10041): Inferred latch for "data[0]" at jiao_tong.vhd(192)
Info (10041): Inferred latch for "data[1]" at jiao_tong.vhd(192)
Info (10041): Inferred latch for "data[2]" at jiao_tong.vhd(192)
Info (10041): Inferred latch for "data[3]" at jiao_tong.vhd(192)
Info: Duplicate registers merged to single register
    Info: Duplicate register "jiao_tong:inst1|g2" merged to single register "jiao_tong:inst1|r2", power-up level changed
Info: State machine "|myjiaotongdeng|jiao_tong:inst1|stx" contains 4 states
Info: Selected Auto state machine encoding method for state machine "|myjiaotongdeng|jiao_tong:inst1|stx"
Info: Encoding result for state machine "|myjiaotongdeng|jiao_tong:inst1|stx"
    Info: Completed encoding using 4 state bits
        Info: Encoded state bit "jiao_tong:inst1|stx.st4"
        Info: Encoded state bit "jiao_tong:inst1|stx.st3"
        Info: Encoded state bit "jiao_tong:inst1|stx.st2"
        Info: Encoded state bit "jiao_tong:inst1|stx.st1"
    Info: State "|myjiaotongdeng|jiao_tong:inst1|stx.st1" uses code string "0000"
    Info: State "|myjiaotongdeng|jiao_tong:inst1|stx.st2" uses code string "0011"
    Info: State "|myjiaotongdeng|jiao_tong:inst1|stx.st3" uses code string "0101"
    Info: State "|myjiaotongdeng|jiao_tong:inst1|stx.st4" uses code string "1001"
Info: Duplicate registers merged to single register
    Info: Duplicate register "jiao_tong:inst1|counter[0]" merged to single register "jiao_tong:inst1|cnt[0]"
Warning (14130): Reduced register "jiao_tong:inst1|cnt[1]" with stuck data_in port to stuck value GND
Warning: LATCH primitive "jiao_tong:inst1|scan[1]" is permanently enabled
Warning: LATCH primitive "jiao_tong:inst1|scan[0]" is permanently enabled
Warning: LATCH primitive "jiao_tong:inst1|data[0]" is permanently enabled
Warning: LATCH primitive "jiao_tong:inst1|data[1]" is permanently enabled
Warning: LATCH primitive "jiao_tong:inst1|data[2]" is permanently enabled
Warning: LATCH primitive "jiao_tong:inst1|data[3]" is permanently enabled
Info: Implemented 115 device resources after synthesis - the final resource count might be different
    Info: Implemented 2 input pins
    Info: Implemented 13 output pins
    Info: Implemented 100 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 9 warnings
    Info: Allocated 162 megabytes of memory during processing
    Info: Processing ended: Mon May 26 14:03:34 2008
    Info: Elapsed time: 00:00:03