myjiaotongdeng.tan.qmsg

本例实现交通灯的控制

{ "Info" "ITDB_TSU_RESULT" "jiao_tong:inst1\|stx.st3 key1 clk -0.442 ns register " "Info: tsu for register \"jiao_tong:inst1\|stx.st3\" (data pin = \"key1\", clock pin = \"clk\") is -0.442 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.611 ns + Longest pin register " "Info: + Longest pin to register delay is 9.611 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.984 ns) 0.984 ns key1 1 PIN PIN_99 21 " "Info: 1: + IC(0.000 ns) + CELL(0.984 ns) = 0.984 ns; Loc. = PIN_99; Fanout = 21; PIN Node = 'key1'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { key1 } "NODE_NAME" } } { "myjiaotongdeng.bdf" "" { Schematic "E:/Altera/myvhdl/myjiaotongdeng/myjiaotongdeng.bdf" { { 200 184 352 216 "key1" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(6.441 ns) + CELL(0.366 ns) 7.791 ns jiao_tong:inst1\|Selector15~91 2 COMB LCCOMB_X22_Y12_N16 4 " "Info: 2: + IC(6.441 ns) + CELL(0.366 ns) = 7.791 ns; Loc. = LCCOMB_X22_Y12_N16; Fanout = 4; COMB Node = 'jiao_tong:inst1\|Selector15~91'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "6.807 ns" { key1 jiao_tong:inst1|Selector15~91 } "NODE_NAME" } } { "jiao_tong.vhd" "" { Text "E:/Altera/myvhdl/myjiaotongdeng/jiao_tong.vhd" 55 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.965 ns) + CELL(0.855 ns) 9.611 ns jiao_tong:inst1\|stx.st3 3 REG LCFF_X20_Y12_N25 7 " "Info: 3: + IC(0.965 ns) + CELL(0.855 ns) = 9.611 ns; Loc. = LCFF_X20_Y12_N25; Fanout = 7; REG Node = 'jiao_tong:inst1\|stx.st3'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.820 ns" { jiao_tong:inst1|Selector15~91 jiao_tong:inst1|stx.st3 } "NODE_NAME" } } { "jiao_tong.vhd" "" { Text "E:/Altera/myvhdl/myjiaotongdeng/jiao_tong.vhd" 50 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.205 ns ( 22.94 % ) " "Info: Total cell delay = 2.205 ns ( 22.94 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.406 ns ( 77.06 % ) " "Info: Total interconnect delay = 7.406 ns ( 77.06 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "9.611 ns" { key1 jiao_tong:inst1|Selector15~91 jiao_tong:inst1|stx.st3 } "NODE_NAME" } } { "e:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/quartus/bin/Technology_Viewer.qrui" "9.611 ns" { key1 {} key1~combout {} jiao_tong:inst1|Selector15~91 {} jiao_tong:inst1|stx.st3 {} } { 0.000ns 0.000ns 6.441ns 0.965ns } { 0.000ns 0.984ns 0.366ns 0.855ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" {  } { { "jiao_tong.vhd" "" { Text "E:/Altera/myvhdl/myjiaotongdeng/jiao_tong.vhd" 50 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 10.013 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 10.013 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns clk 1 CLK PIN_23 2 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 2; CLK Node = 'clk'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "myjiaotongdeng.bdf" "" { Schematic "E:/Altera/myvhdl/myjiaotongdeng/myjiaotongdeng.bdf" { { 144 232 400 160 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.324 ns) + CELL(0.970 ns) 3.434 ns jiao_tong:inst1\|clk1khz 2 REG LCFF_X5_Y5_N21 3 " "Info: 2: + IC(1.324 ns) + CELL(0.970 ns) = 3.434 ns; Loc. = LCFF_X5_Y5_N21; Fanout = 3; REG Node = 'jiao_tong:inst1\|clk1khz'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.294 ns" { clk jiao_tong:inst1|clk1khz } "NODE_NAME" } } { "jiao_tong.vhd" "" { Text "E:/Altera/myvhdl/myjiaotongdeng/jiao_tong.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.164 ns) + CELL(0.970 ns) 6.568 ns jiao_tong:inst1\|clk1hz 3 REG LCFF_X22_Y6_N25 9 " "Info: 3: + IC(2.164 ns) + CELL(0.970 ns) = 6.568 ns; Loc. = LCFF_X22_Y6_N25; Fanout = 9; REG Node = 'jiao_tong:inst1\|clk1hz'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "3.134 ns" { jiao_tong:inst1|clk1khz jiao_tong:inst1|clk1hz } "NODE_NAME" } } { "jiao_tong.vhd" "" { Text "E:/Altera/myvhdl/myjiaotongdeng/jiao_tong.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.919 ns) + CELL(0.000 ns) 8.487 ns jiao_tong:inst1\|clk1hz~clkctrl 4 COMB CLKCTRL_G5 16 " "Info: 4: + IC(1.919 ns) + CELL(0.000 ns) = 8.487 ns; Loc. = CLKCTRL_G5; Fanout = 16; COMB Node = 'jiao_tong:inst1\|clk1hz~clkctrl'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.919 ns" { jiao_tong:inst1|clk1hz jiao_tong:inst1|clk1hz~clkctrl } "NODE_NAME" } } { "jiao_tong.vhd" "" { Text "E:/Altera/myvhdl/myjiaotongdeng/jiao_tong.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.860 ns) + CELL(0.666 ns) 10.013 ns jiao_tong:inst1\|stx.st3 5 REG LCFF_X20_Y12_N25 7 " "Info: 5: + IC(0.860 ns) + CELL(0.666 ns) = 10.013 ns; Loc. = LCFF_X20_Y12_N25; Fanout = 7; REG Node = 'jiao_tong:inst1\|stx.st3'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.526 ns" { jiao_tong:inst1|clk1hz~clkctrl jiao_tong:inst1|stx.st3 } "NODE_NAME" } } { "jiao_tong.vhd" "" { Text "E:/Altera/myvhdl/myjiaotongdeng/jiao_tong.vhd" 50 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.746 ns ( 37.41 % ) " "Info: Total cell delay = 3.746 ns ( 37.41 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.267 ns ( 62.59 % ) " "Info: Total interconnect delay = 6.267 ns ( 62.59 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "10.013 ns" { clk jiao_tong:inst1|clk1khz jiao_tong:inst1|clk1hz jiao_tong:inst1|clk1hz~clkctrl jiao_tong:inst1|stx.st3 } "NODE_NAME" } } { "e:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/quartus/bin/Technology_Viewer.qrui" "10.013 ns" { clk {} clk~combout {} jiao_tong:inst1|clk1khz {} jiao_tong:inst1|clk1hz {} jiao_tong:inst1|clk1hz~clkctrl {} jiao_tong:inst1|stx.st3 {} } { 0.000ns 0.000ns 1.324ns 2.164ns 1.919ns 0.860ns } { 0.000ns 1.140ns 0.970ns 0.970ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "9.611 ns" { key1 jiao_tong:inst1|Selector15~91 jiao_tong:inst1|stx.st3 } "NODE_NAME" } } { "e:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/quartus/bin/Technology_Viewer.qrui" "9.611 ns" { key1 {} key1~combout {} jiao_tong:inst1|Selector15~91 {} jiao_tong:inst1|stx.st3 {} } { 0.000ns 0.000ns 6.441ns 0.965ns } { 0.000ns 0.984ns 0.366ns 0.855ns } "" } } { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "10.013 ns" { clk jiao_tong:inst1|clk1khz jiao_tong:inst1|clk1hz jiao_tong:inst1|clk1hz~clkctrl jiao_tong:inst1|stx.st3 } "NODE_NAME" } } { "e:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/quartus/bin/Technology_Viewer.qrui" "10.013 ns" { clk {} clk~combout {} jiao_tong:inst1|clk1khz {} jiao_tong:inst1|clk1hz {} jiao_tong:inst1|clk1hz~clkctrl {} jiao_tong:inst1|stx.st3 {} } { 0.000ns 0.000ns 1.324ns 2.164ns 1.919ns 0.860ns } { 0.000ns 1.140ns 0.970ns 0.970ns 0.000ns 0.666ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk 78leddata\[5\] jiao_tong:inst1\|q1\[1\] 20.142 ns register " "Info: tco from clock \"clk\" to destination pin \"78leddata\[5\]\" through register \"jiao_tong:inst1\|q1\[1\]\" is 20.142 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 10.014 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 10.014 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns clk 1 CLK PIN_23 2 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 2; CLK Node = 'clk'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "myjiaotongdeng.bdf" "" { Schematic "E:/Altera/myvhdl/myjiaotongdeng/myjiaotongdeng.bdf" { { 144 232 400 160 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.324 ns) + CELL(0.970 ns) 3.434 ns jiao_tong:inst1\|clk1khz 2 REG LCFF_X5_Y5_N21 3 " "Info: 2: + IC(1.324 ns) + CELL(0.970 ns) = 3.434 ns; Loc. = LCFF_X5_Y5_N21; Fanout = 3; REG Node = 'jiao_tong:inst1\|clk1khz'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.294 ns" { clk jiao_tong:inst1|clk1khz } "NODE_NAME" } } { "jiao_tong.vhd" "" { Text "E:/Altera/myvhdl/myjiaotongdeng/jiao_tong.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.164 ns) + CELL(0.970 ns) 6.568 ns jiao_tong:inst1\|clk1hz 3 REG LCFF_X22_Y6_N25 9 " "Info: 3: + IC(2.164 ns) + CELL(0.970 ns) = 6.568 ns; Loc. = LCFF_X22_Y6_N25; Fanout = 9; REG Node = 'jiao_tong:inst1\|clk1hz'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "3.134 ns" { jiao_tong:inst1|clk1khz jiao_tong:inst1|clk1hz } "NODE_NAME" } } { "jiao_tong.vhd" "" { Text "E:/Altera/myvhdl/myjiaotongdeng/jiao_tong.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.919 ns) + CELL(0.000 ns) 8.487 ns jiao_tong:inst1\|clk1hz~clkctrl 4 COMB CLKCTRL_G5 16 " "Info: 4: + IC(1.919 ns) + CELL(0.000 ns) = 8.487 ns; Loc. = CLKCTRL_G5; Fanout = 16; COMB Node = 'jiao_tong:inst1\|clk1hz~clkctrl'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.919 ns" { jiao_tong:inst1|clk1hz jiao_tong:inst1|clk1hz~clkctrl } "NODE_NAME" } } { "jiao_tong.vhd" "" { Text "E:/Altera/myvhdl/myjiaotongdeng/jiao_tong.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.861 ns) + CELL(0.666 ns) 10.014 ns jiao_tong:inst1\|q1\[1\] 5 REG LCFF_X21_Y12_N17 6 " "Info: 5: + IC(0.861 ns) + CELL(0.666 ns) = 10.014 ns; Loc. = LCFF_X21_Y12_N17; Fanout = 6; REG Node = 'jiao_tong:inst1\|q1\[1\]'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.527 ns" { jiao_tong:inst1|clk1hz~clkctrl jiao_tong:inst1|q1[1] } "NODE_NAME" } } { "jiao_tong.vhd" "" { Text "E:/Altera/myvhdl/myjiaotongdeng/jiao_tong.vhd" 54 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.746 ns ( 37.41 % ) " "Info: Total cell delay = 3.746 ns ( 37.41 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.268 ns ( 62.59 % ) " "Info: Total interconnect delay = 6.268 ns ( 62.59 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "10.014 ns" { clk jiao_tong:inst1|clk1khz jiao_tong:inst1|clk1hz jiao_tong:inst1|clk1hz~clkctrl jiao_tong:inst1|q1[1] } "NODE_NAME" } } { "e:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/quartus/bin/Technology_Viewer.qrui" "10.014 ns" { clk {} clk~combout {} jiao_tong:inst1|clk1khz {} jiao_tong:inst1|clk1hz {} jiao_tong:inst1|clk1hz~clkctrl {} jiao_tong:inst1|q1[1] {} } { 0.000ns 0.000ns 1.324ns 2.164ns 1.919ns 0.861ns } { 0.000ns 1.140ns 0.970ns 0.970ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" {  } { { "jiao_tong.vhd" "" { Text "E:/Altera/myvhdl/myjiaotongdeng/jiao_tong.vhd" 54 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.824 ns + Longest register pin " "Info: + Longest register to pin delay is 9.824 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns jiao_tong:inst1\|q1\[1\] 1 REG LCFF_X21_Y12_N17 6 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X21_Y12_N17; Fanout = 6; REG Node = 'jiao_tong:inst1\|q1\[1\]'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { jiao_tong:inst1|q1[1] } "NODE_NAME" } } { "jiao_tong.vhd" "" { Text "E:/Altera/myvhdl/myjiaotongdeng/jiao_tong.vhd" 54 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.188 ns) + CELL(0.647 ns) 1.835 ns jiao_tong:inst1\|Mux2~15 2 COMB LCCOMB_X22_Y12_N12 7 " "Info: 2: + IC(1.188 ns) + CELL(0.647 ns) = 1.835 ns; Loc. = LCCOMB_X22_Y12_N12; Fanout = 7; COMB Node = 'jiao_tong:inst1\|Mux2~15'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.835 ns" { jiao_tong:inst1|q1[1] jiao_tong:inst1|Mux2~15 } "NODE_NAME" } } { "jiao_tong.vhd" "" { Text "E:/Altera/myvhdl/myjiaotongdeng/jiao_tong.vhd" 194 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.575 ns) + CELL(0.615 ns) 4.025 ns jiao_tong:inst1\|Mux8~13 3 COMB LCCOMB_X22_Y6_N8 1 " "Info: 3: + IC(1.575 ns) + CELL(0.615 ns) = 4.025 ns; Loc. = LCCOMB_X22_Y6_N8; Fanout = 1; COMB Node = 'jiao_tong:inst1\|Mux8~13'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.190 ns" { jiao_tong:inst1|Mux2~15 jiao_tong:inst1|Mux8~13 } "NODE_NAME" } } { "jiao_tong.vhd" "" { Text "E:/Altera/myvhdl/myjiaotongdeng/jiao_tong.vhd" 203 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.357 ns) + CELL(0.624 ns) 5.006 ns jiao_tong:inst1\|seg7\[5\]~280 4 COMB LCCOMB_X22_Y6_N4 1 " "Info: 4: + IC(0.357 ns) + CELL(0.624 ns) = 5.006 ns; Loc. = LCCOMB_X22_Y6_N4; Fanout = 1; COMB Node = 'jiao_tong:inst1\|seg7\[5\]~280'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.981 ns" { jiao_tong:inst1|Mux8~13 jiao_tong:inst1|seg7[5]~280 } "NODE_NAME" } } { "jiao_tong.vhd" "" { Text "E:/Altera/myvhdl/myjiaotongdeng/jiao_tong.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.722 ns) + CELL(3.096 ns) 9.824 ns 78leddata\[5\] 5 PIN PIN_134 0 " "Info: 5: + IC(1.722 ns) + CELL(3.096 ns) = 9.824 ns; Loc. = PIN_134; Fanout = 0; PIN Node = '78leddata\[5\]'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "4.818 ns" { jiao_tong:inst1|seg7[5]~280 78leddata[5] } "NODE_NAME" } } { "myjiaotongdeng.bdf" "" { Schematic "E:/Altera/myvhdl/myjiaotongdeng/myjiaotongdeng.bdf" { { 160 656 832 176 "78leddata\[6..0\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.982 ns ( 50.71 % ) " "Info: Total cell delay = 4.982 ns ( 50.71 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.842 ns ( 49.29 % ) " "Info: Total interconnect delay = 4.842 ns ( 49.29 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "9.824 ns" { jiao_tong:inst1|q1[1] jiao_tong:inst1|Mux2~15 jiao_tong:inst1|Mux8~13 jiao_tong:inst1|seg7[5]~280 78leddata[5] } "NODE_NAME" } } { "e:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/quartus/bin/Technology_Viewer.qrui" "9.824 ns" { jiao_tong:inst1|q1[1] {} jiao_tong:inst1|Mux2~15 {} jiao_tong:inst1|Mux8~13 {} jiao_tong:inst1|seg7[5]~280 {} 78leddata[5] {} } { 0.000ns 1.188ns 1.575ns 0.357ns 1.722ns } { 0.000ns 0.647ns 0.615ns 0.624ns 3.096ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "10.014 ns" { clk jiao_tong:inst1|clk1khz jiao_tong:inst1|clk1hz jiao_tong:inst1|clk1hz~clkctrl jiao_tong:inst1|q1[1] } "NODE_NAME" } } { "e:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/quartus/bin/Technology_Viewer.qrui" "10.014 ns" { clk {} clk~combout {} jiao_tong:inst1|clk1khz {} jiao_tong:inst1|clk1hz {} jiao_tong:inst1|clk1hz~clkctrl {} jiao_tong:inst1|q1[1] {} } { 0.000ns 0.000ns 1.324ns 2.164ns 1.919ns 0.861ns } { 0.000ns 1.140ns 0.970ns 0.970ns 0.000ns 0.666ns } "" } } { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "9.824 ns" { jiao_tong:inst1|q1[1] jiao_tong:inst1|Mux2~15 jiao_tong:inst1|Mux8~13 jiao_tong:inst1|seg7[5]~280 78leddata[5] } "NODE_NAME" } } { "e:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/quartus/bin/Technology_Viewer.qrui" "9.824 ns" { jiao_tong:inst1|q1[1] {} jiao_tong:inst1|Mux2~15 {} jiao_tong:inst1|Mux8~13 {} jiao_tong:inst1|seg7[5]~280 {} 78leddata[5] {} } { 0.000ns 1.188ns 1.575ns 0.357ns 1.722ns } { 0.000ns 0.647ns 0.615ns 0.624ns 3.096ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "key1 led3 14.070 ns Longest " "Info: Longest tpd from source pin \"key1\" to destination pin \"led3\" is 14.070 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.984 ns) 0.984 ns key1 1 PIN PIN_99 21 " "Info: 1: + IC(0.000 ns) + CELL(0.984 ns) = 0.984 ns; Loc. = PIN_99; Fanout = 21; PIN Node = 'key1'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { key1 } "NODE_NAME" } } { "myjiaotongdeng.bdf" "" { Schematic "E:/Altera/myvhdl/myjiaotongdeng/myjiaotongdeng.bdf" { { 200 184 352 216 "key1" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(6.446 ns) + CELL(0.370 ns) 7.800 ns jiao_tong:inst1\|rb~4 2 COMB LCCOMB_X22_Y12_N6 2 " "Info: 2: + IC(6.446 ns) + CELL(0.370 ns) = 7.800 ns; Loc. = LCCOMB_X22_Y12_N6; Fanout = 2; COMB Node = 'jiao_tong:inst1\|rb~4'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "6.816 ns" { key1 jiao_tong:inst1|rb~4 } "NODE_NAME" } } { "jiao_tong.vhd" "" { Text "E:/Altera/myvhdl/myjiaotongdeng/jiao_tong.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.134 ns) + CELL(3.136 ns) 14.070 ns led3 3 PIN PIN_4 0 " "Info: 3: + IC(3.134 ns) + CELL(3.136 ns) = 14.070 ns; Loc. = PIN_4; Fanout = 0; PIN Node = 'led3'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "6.270 ns" { jiao_tong:inst1|rb~4 led3 } "NODE_NAME" } } { "myjiaotongdeng.bdf" "" { Schematic "E:/Altera/myvhdl/myjiaotongdeng/myjiaotongdeng.bdf" { { 256 656 832 272 "led3" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.490 ns ( 31.91 % ) " "Info: Total cell delay = 4.490 ns ( 31.91 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "9.580 ns ( 68.09 % ) " "Info: Total interconnect delay = 9.580 ns ( 68.09 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "14.070 ns" { key1 jiao_tong:inst1|rb~4 led3 } "NODE_NAME" } } { "e:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/quartus/bin/Technology_Viewer.qrui" "14.070 ns" { key1 {} key1~combout {} jiao_tong:inst1|rb~4 {} led3 {} } { 0.000ns 0.000ns 6.446ns 3.134ns } { 0.000ns 0.984ns 0.370ns 3.136ns } "" } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0 "" 0}