prev_cmp_myjiaotongdeng.tan.qmsg

本例实现交通灯的控制

{ "Info" "ITDB_TH_RESULT" "jiao_tong:inst1\|q1\[2\] key1 clk 1.879 ns register " "Info: th for register \"jiao_tong:inst1\|q1\[2\]\" (data pin = \"key1\", clock pin = \"clk\") is 1.879 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 9.670 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 9.670 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns clk 1 CLK PIN_23 2 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 2; CLK Node = 'clk'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "myjiaotongdeng.bdf" "" { Schematic "E:/Altera/myvhdl/myjiaotongdeng/myjiaotongdeng.bdf" { { 144 232 400 160 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.011 ns) + CELL(0.970 ns) 4.121 ns jiao_tong:inst1\|clk1khz 2 REG LCFF_X21_Y12_N17 3 " "Info: 2: + IC(2.011 ns) + CELL(0.970 ns) = 4.121 ns; Loc. = LCFF_X21_Y12_N17; Fanout = 3; REG Node = 'jiao_tong:inst1\|clk1khz'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.981 ns" { clk jiao_tong:inst1|clk1khz } "NODE_NAME" } } { "jiao_tong.vhd" "" { Text "E:/Altera/myvhdl/myjiaotongdeng/jiao_tong.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.113 ns) + CELL(0.970 ns) 6.204 ns jiao_tong:inst1\|clk1hz 3 REG LCFF_X21_Y9_N15 9 " "Info: 3: + IC(1.113 ns) + CELL(0.970 ns) = 6.204 ns; Loc. = LCFF_X21_Y9_N15; Fanout = 9; REG Node = 'jiao_tong:inst1\|clk1hz'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.083 ns" { jiao_tong:inst1|clk1khz jiao_tong:inst1|clk1hz } "NODE_NAME" } } { "jiao_tong.vhd" "" { Text "E:/Altera/myvhdl/myjiaotongdeng/jiao_tong.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.948 ns) + CELL(0.000 ns) 8.152 ns jiao_tong:inst1\|clk1hz~clkctrl 4 COMB CLKCTRL_G6 16 " "Info: 4: + IC(1.948 ns) + CELL(0.000 ns) = 8.152 ns; Loc. = CLKCTRL_G6; Fanout = 16; COMB Node = 'jiao_tong:inst1\|clk1hz~clkctrl'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.948 ns" { jiao_tong:inst1|clk1hz jiao_tong:inst1|clk1hz~clkctrl } "NODE_NAME" } } { "jiao_tong.vhd" "" { Text "E:/Altera/myvhdl/myjiaotongdeng/jiao_tong.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.852 ns) + CELL(0.666 ns) 9.670 ns jiao_tong:inst1\|q1\[2\] 5 REG LCFF_X24_Y9_N11 5 " "Info: 5: + IC(0.852 ns) + CELL(0.666 ns) = 9.670 ns; Loc. = LCFF_X24_Y9_N11; Fanout = 5; REG Node = 'jiao_tong:inst1\|q1\[2\]'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.518 ns" { jiao_tong:inst1|clk1hz~clkctrl jiao_tong:inst1|q1[2] } "NODE_NAME" } } { "jiao_tong.vhd" "" { Text "E:/Altera/myvhdl/myjiaotongdeng/jiao_tong.vhd" 54 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.746 ns ( 38.74 % ) " "Info: Total cell delay = 3.746 ns ( 38.74 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.924 ns ( 61.26 % ) " "Info: Total interconnect delay = 5.924 ns ( 61.26 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "9.670 ns" { clk jiao_tong:inst1|clk1khz jiao_tong:inst1|clk1hz jiao_tong:inst1|clk1hz~clkctrl jiao_tong:inst1|q1[2] } "NODE_NAME" } } { "e:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/quartus/bin/Technology_Viewer.qrui" "9.670 ns" { clk {} clk~combout {} jiao_tong:inst1|clk1khz {} jiao_tong:inst1|clk1hz {} jiao_tong:inst1|clk1hz~clkctrl {} jiao_tong:inst1|q1[2] {} } { 0.000ns 0.000ns 2.011ns 1.113ns 1.948ns 0.852ns } { 0.000ns 1.140ns 0.970ns 0.970ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.306 ns + " "Info: + Micro hold delay of destination is 0.306 ns" {  } { { "jiao_tong.vhd" "" { Text "E:/Altera/myvhdl/myjiaotongdeng/jiao_tong.vhd" 54 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.097 ns - Shortest pin register " "Info: - Shortest pin to register delay is 8.097 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.994 ns) 0.994 ns key1 1 PIN PIN_97 20 " "Info: 1: + IC(0.000 ns) + CELL(0.994 ns) = 0.994 ns; Loc. = PIN_97; Fanout = 20; PIN Node = 'key1'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { key1 } "NODE_NAME" } } { "myjiaotongdeng.bdf" "" { Schematic "E:/Altera/myvhdl/myjiaotongdeng/myjiaotongdeng.bdf" { { 200 208 376 216 "key1" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(6.248 ns) + CELL(0.855 ns) 8.097 ns jiao_tong:inst1\|q1\[2\] 2 REG LCFF_X24_Y9_N11 5 " "Info: 2: + IC(6.248 ns) + CELL(0.855 ns) = 8.097 ns; Loc. = LCFF_X24_Y9_N11; Fanout = 5; REG Node = 'jiao_tong:inst1\|q1\[2\]'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "7.103 ns" { key1 jiao_tong:inst1|q1[2] } "NODE_NAME" } } { "jiao_tong.vhd" "" { Text "E:/Altera/myvhdl/myjiaotongdeng/jiao_tong.vhd" 54 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.849 ns ( 22.84 % ) " "Info: Total cell delay = 1.849 ns ( 22.84 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.248 ns ( 77.16 % ) " "Info: Total interconnect delay = 6.248 ns ( 77.16 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "8.097 ns" { key1 jiao_tong:inst1|q1[2] } "NODE_NAME" } } { "e:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/quartus/bin/Technology_Viewer.qrui" "8.097 ns" { key1 {} key1~combout {} jiao_tong:inst1|q1[2] {} } { 0.000ns 0.000ns 6.248ns } { 0.000ns 0.994ns 0.855ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "9.670 ns" { clk jiao_tong:inst1|clk1khz jiao_tong:inst1|clk1hz jiao_tong:inst1|clk1hz~clkctrl jiao_tong:inst1|q1[2] } "NODE_NAME" } } { "e:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/quartus/bin/Technology_Viewer.qrui" "9.670 ns" { clk {} clk~combout {} jiao_tong:inst1|clk1khz {} jiao_tong:inst1|clk1hz {} jiao_tong:inst1|clk1hz~clkctrl {} jiao_tong:inst1|q1[2] {} } { 0.000ns 0.000ns 2.011ns 1.113ns 1.948ns 0.852ns } { 0.000ns 1.140ns 0.970ns 0.970ns 0.000ns 0.666ns } "" } } { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "8.097 ns" { key1 jiao_tong:inst1|q1[2] } "NODE_NAME" } } { "e:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/quartus/bin/Technology_Viewer.qrui" "8.097 ns" { key1 {} key1~combout {} jiao_tong:inst1|q1[2] {} } { 0.000ns 0.000ns 6.248ns } { 0.000ns 0.994ns 0.855ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 2 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "114 " "Info: Allocated 114 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Mon May 26 14:01:02 2008 " "Info: Processing ended: Mon May 26 14:01:02 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}