prev_cmp_myjiaotongdeng.tan.qmsg

本例实现交通灯的控制

{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "myjiaotongdeng.bdf" "" { Schematic "E:/Altera/myvhdl/myjiaotongdeng/myjiaotongdeng.bdf" { { 144 232 400 160 "clk" "" } } } } { "e:/altera/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "2 " "Warning: Found 2 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "jiao_tong:inst1\|clk1hz " "Info: Detected ripple clock \"jiao_tong:inst1\|clk1hz\" as buffer" {  } { { "jiao_tong.vhd" "" { Text "E:/Altera/myvhdl/myjiaotongdeng/jiao_tong.vhd" 15 -1 0 } } { "e:/altera/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus/bin/Assignment Editor.qase" 1 { { 0 "jiao_tong:inst1\|clk1hz" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "jiao_tong:inst1\|clk1khz " "Info: Detected ripple clock \"jiao_tong:inst1\|clk1khz\" as buffer" {  } { { "jiao_tong.vhd" "" { Text "E:/Altera/myvhdl/myjiaotongdeng/jiao_tong.vhd" 15 -1 0 } } { "e:/altera/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus/bin/Assignment Editor.qase" 1 { { 0 "jiao_tong:inst1\|clk1khz" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0 "" 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register jiao_tong:inst1\|counter\[1\] register jiao_tong:inst1\|clk1hz 210.79 MHz 4.744 ns Internal " "Info: Clock \"clk\" has Internal fmax of 210.79 MHz between source register \"jiao_tong:inst1\|counter\[1\]\" and destination register \"jiao_tong:inst1\|clk1hz\" (period= 4.744 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.828 ns + Longest register register " "Info: + Longest register to register delay is 2.828 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns jiao_tong:inst1\|counter\[1\] 1 REG LCFF_X20_Y9_N3 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X20_Y9_N3; Fanout = 3; REG Node = 'jiao_tong:inst1\|counter\[1\]'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { jiao_tong:inst1|counter[1] } "NODE_NAME" } } { "jiao_tong.vhd" "" { Text "E:/Altera/myvhdl/myjiaotongdeng/jiao_tong.vhd" 39 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.780 ns) + CELL(0.646 ns) 1.426 ns jiao_tong:inst1\|Equal1~80 2 COMB LCCOMB_X20_Y9_N18 7 " "Info: 2: + IC(0.780 ns) + CELL(0.646 ns) = 1.426 ns; Loc. = LCCOMB_X20_Y9_N18; Fanout = 7; COMB Node = 'jiao_tong:inst1\|Equal1~80'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.426 ns" { jiao_tong:inst1|counter[1] jiao_tong:inst1|Equal1~80 } "NODE_NAME" } } { "jiao_tong.vhd" "" { Text "E:/Altera/myvhdl/myjiaotongdeng/jiao_tong.vhd" 40 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.670 ns) + CELL(0.624 ns) 2.720 ns jiao_tong:inst1\|clk1hz~42 3 COMB LCCOMB_X21_Y9_N14 1 " "Info: 3: + IC(0.670 ns) + CELL(0.624 ns) = 2.720 ns; Loc. = LCCOMB_X21_Y9_N14; Fanout = 1; COMB Node = 'jiao_tong:inst1\|clk1hz~42'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.294 ns" { jiao_tong:inst1|Equal1~80 jiao_tong:inst1|clk1hz~42 } "NODE_NAME" } } { "jiao_tong.vhd" "" { Text "E:/Altera/myvhdl/myjiaotongdeng/jiao_tong.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 2.828 ns jiao_tong:inst1\|clk1hz 4 REG LCFF_X21_Y9_N15 9 " "Info: 4: + IC(0.000 ns) + CELL(0.108 ns) = 2.828 ns; Loc. = LCFF_X21_Y9_N15; Fanout = 9; REG Node = 'jiao_tong:inst1\|clk1hz'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.108 ns" { jiao_tong:inst1|clk1hz~42 jiao_tong:inst1|clk1hz } "NODE_NAME" } } { "jiao_tong.vhd" "" { Text "E:/Altera/myvhdl/myjiaotongdeng/jiao_tong.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.378 ns ( 48.73 % ) " "Info: Total cell delay = 1.378 ns ( 48.73 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.450 ns ( 51.27 % ) " "Info: Total interconnect delay = 1.450 ns ( 51.27 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.828 ns" { jiao_tong:inst1|counter[1] jiao_tong:inst1|Equal1~80 jiao_tong:inst1|clk1hz~42 jiao_tong:inst1|clk1hz } "NODE_NAME" } } { "e:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/quartus/bin/Technology_Viewer.qrui" "2.828 ns" { jiao_tong:inst1|counter[1] {} jiao_tong:inst1|Equal1~80 {} jiao_tong:inst1|clk1hz~42 {} jiao_tong:inst1|clk1hz {} } { 0.000ns 0.780ns 0.670ns 0.000ns } { 0.000ns 0.646ns 0.624ns 0.108ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-1.652 ns - Smallest " "Info: - Smallest clock skew is -1.652 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 5.900 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 5.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns clk 1 CLK PIN_23 2 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 2; CLK Node = 'clk'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "myjiaotongdeng.bdf" "" { Schematic "E:/Altera/myvhdl/myjiaotongdeng/myjiaotongdeng.bdf" { { 144 232 400 160 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.011 ns) + CELL(0.970 ns) 4.121 ns jiao_tong:inst1\|clk1khz 2 REG LCFF_X21_Y12_N17 3 " "Info: 2: + IC(2.011 ns) + CELL(0.970 ns) = 4.121 ns; Loc. = LCFF_X21_Y12_N17; Fanout = 3; REG Node = 'jiao_tong:inst1\|clk1khz'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.981 ns" { clk jiao_tong:inst1|clk1khz } "NODE_NAME" } } { "jiao_tong.vhd" "" { Text "E:/Altera/myvhdl/myjiaotongdeng/jiao_tong.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.113 ns) + CELL(0.666 ns) 5.900 ns jiao_tong:inst1\|clk1hz 3 REG LCFF_X21_Y9_N15 9 " "Info: 3: + IC(1.113 ns) + CELL(0.666 ns) = 5.900 ns; Loc. = LCFF_X21_Y9_N15; Fanout = 9; REG Node = 'jiao_tong:inst1\|clk1hz'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.779 ns" { jiao_tong:inst1|clk1khz jiao_tong:inst1|clk1hz } "NODE_NAME" } } { "jiao_tong.vhd" "" { Text "E:/Altera/myvhdl/myjiaotongdeng/jiao_tong.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.776 ns ( 47.05 % ) " "Info: Total cell delay = 2.776 ns ( 47.05 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.124 ns ( 52.95 % ) " "Info: Total interconnect delay = 3.124 ns ( 52.95 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "5.900 ns" { clk jiao_tong:inst1|clk1khz jiao_tong:inst1|clk1hz } "NODE_NAME" } } { "e:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/quartus/bin/Technology_Viewer.qrui" "5.900 ns" { clk {} clk~combout {} jiao_tong:inst1|clk1khz {} jiao_tong:inst1|clk1hz {} } { 0.000ns 0.000ns 2.011ns 1.113ns } { 0.000ns 1.140ns 0.970ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 7.552 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 7.552 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns clk 1 CLK PIN_23 2 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 2; CLK Node = 'clk'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "myjiaotongdeng.bdf" "" { Schematic "E:/Altera/myvhdl/myjiaotongdeng/myjiaotongdeng.bdf" { { 144 232 400 160 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.011 ns) + CELL(0.970 ns) 4.121 ns jiao_tong:inst1\|clk1khz 2 REG LCFF_X21_Y12_N17 3 " "Info: 2: + IC(2.011 ns) + CELL(0.970 ns) = 4.121 ns; Loc. = LCFF_X21_Y12_N17; Fanout = 3; REG Node = 'jiao_tong:inst1\|clk1khz'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.981 ns" { clk jiao_tong:inst1|clk1khz } "NODE_NAME" } } { "jiao_tong.vhd" "" { Text "E:/Altera/myvhdl/myjiaotongdeng/jiao_tong.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.917 ns) + CELL(0.000 ns) 6.038 ns jiao_tong:inst1\|clk1khz~clkctrl 3 COMB CLKCTRL_G7 9 " "Info: 3: + IC(1.917 ns) + CELL(0.000 ns) = 6.038 ns; Loc. = CLKCTRL_G7; Fanout = 9; COMB Node = 'jiao_tong:inst1\|clk1khz~clkctrl'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.917 ns" { jiao_tong:inst1|clk1khz jiao_tong:inst1|clk1khz~clkctrl } "NODE_NAME" } } { "jiao_tong.vhd" "" { Text "E:/Altera/myvhdl/myjiaotongdeng/jiao_tong.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.848 ns) + CELL(0.666 ns) 7.552 ns jiao_tong:inst1\|counter\[1\] 4 REG LCFF_X20_Y9_N3 3 " "Info: 4: + IC(0.848 ns) + CELL(0.666 ns) = 7.552 ns; Loc. = LCFF_X20_Y9_N3; Fanout = 3; REG Node = 'jiao_tong:inst1\|counter\[1\]'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.514 ns" { jiao_tong:inst1|clk1khz~clkctrl jiao_tong:inst1|counter[1] } "NODE_NAME" } } { "jiao_tong.vhd" "" { Text "E:/Altera/myvhdl/myjiaotongdeng/jiao_tong.vhd" 39 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.776 ns ( 36.76 % ) " "Info: Total cell delay = 2.776 ns ( 36.76 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.776 ns ( 63.24 % ) " "Info: Total interconnect delay = 4.776 ns ( 63.24 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "7.552 ns" { clk jiao_tong:inst1|clk1khz jiao_tong:inst1|clk1khz~clkctrl jiao_tong:inst1|counter[1] } "NODE_NAME" } } { "e:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/quartus/bin/Technology_Viewer.qrui" "7.552 ns" { clk {} clk~combout {} jiao_tong:inst1|clk1khz {} jiao_tong:inst1|clk1khz~clkctrl {} jiao_tong:inst1|counter[1] {} } { 0.000ns 0.000ns 2.011ns 1.917ns 0.848ns } { 0.000ns 1.140ns 0.970ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "5.900 ns" { clk jiao_tong:inst1|clk1khz jiao_tong:inst1|clk1hz } "NODE_NAME" } } { "e:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/quartus/bin/Technology_Viewer.qrui" "5.900 ns" { clk {} clk~combout {} jiao_tong:inst1|clk1khz {} jiao_tong:inst1|clk1hz {} } { 0.000ns 0.000ns 2.011ns 1.113ns } { 0.000ns 1.140ns 0.970ns 0.666ns } "" } } { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "7.552 ns" { clk jiao_tong:inst1|clk1khz jiao_tong:inst1|clk1khz~clkctrl jiao_tong:inst1|counter[1] } "NODE_NAME" } } { "e:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/quartus/bin/Technology_Viewer.qrui" "7.552 ns" { clk {} clk~combout {} jiao_tong:inst1|clk1khz {} jiao_tong:inst1|clk1khz~clkctrl {} jiao_tong:inst1|counter[1] {} } { 0.000ns 0.000ns 2.011ns 1.917ns 0.848ns } { 0.000ns 1.140ns 0.970ns 0.000ns 0.666ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" {  } { { "jiao_tong.vhd" "" { Text "E:/Altera/myvhdl/myjiaotongdeng/jiao_tong.vhd" 39 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" {  } { { "jiao_tong.vhd" "" { Text "E:/Altera/myvhdl/myjiaotongdeng/jiao_tong.vhd" 15 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.828 ns" { jiao_tong:inst1|counter[1] jiao_tong:inst1|Equal1~80 jiao_tong:inst1|clk1hz~42 jiao_tong:inst1|clk1hz } "NODE_NAME" } } { "e:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/quartus/bin/Technology_Viewer.qrui" "2.828 ns" { jiao_tong:inst1|counter[1] {} jiao_tong:inst1|Equal1~80 {} jiao_tong:inst1|clk1hz~42 {} jiao_tong:inst1|clk1hz {} } { 0.000ns 0.780ns 0.670ns 0.000ns } { 0.000ns 0.646ns 0.624ns 0.108ns } "" } } { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "5.900 ns" { clk jiao_tong:inst1|clk1khz jiao_tong:inst1|clk1hz } "NODE_NAME" } } { "e:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/quartus/bin/Technology_Viewer.qrui" "5.900 ns" { clk {} clk~combout {} jiao_tong:inst1|clk1khz {} jiao_tong:inst1|clk1hz {} } { 0.000ns 0.000ns 2.011ns 1.113ns } { 0.000ns 1.140ns 0.970ns 0.666ns } "" } } { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "7.552 ns" { clk jiao_tong:inst1|clk1khz jiao_tong:inst1|clk1khz~clkctrl jiao_tong:inst1|counter[1] } "NODE_NAME" } } { "e:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/quartus/bin/Technology_Viewer.qrui" "7.552 ns" { clk {} clk~combout {} jiao_tong:inst1|clk1khz {} jiao_tong:inst1|clk1khz~clkctrl {} jiao_tong:inst1|counter[1] {} } { 0.000ns 0.000ns 2.011ns 1.917ns 0.848ns } { 0.000ns 1.140ns 0.970ns 0.000ns 0.666ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}