📄 2.txt
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entity count is
Port ( clk : in STD_LOGIC;
reset : in STD_LOGIC;
clkout : out STD_LOGIC;
s1 : out STD_LOGIC;
s2 : out STD_LOGIC);
end count;
architecture Behavioral of count is
signal s1n,s2n : std_logic;
signal cnt : integer range 0 to 4;
begin
process(clk,reset)
begin
if reset='1' then
cnt<=0;
elsif clk'event and clk='1' then
if cnt=4 then
cnt<=0;
else
cnt<=cnt+1;
end if;
end if;
end process;
p1:process(clk,reset)
begin
if reset='1' then
s1n<='0';
elsif clk'event and clk='1' then
if cnt=0 then
s1n<=not s1n;
else
s1n<=s1n;
end if;
end if;
end process;
p2:process(clk,reset)
begin
if reset='1' then
s2n<='0';
elsif clk'event and clk='0' then
if cnt=3 then
s2n<=not s2n;
else
s2n<=s2n;
end if;
end if;
s1<=s1n;
s2<=s2n;
end process;
clkout<= s1n xor s2n;
end Behavioral;
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