smsc9118.h

SMSC LAN device linux Uboot code

//--------------------------------------------------------------------------
//
// File name:      smsc9118.h
//
// Abstract:      Address map and register definitions for SMSC LAN9118
//          ethernet controller.
//
// Start Automated RH
// *** Do not edit between "Start Automated RH" and "End Automated RH" ***
//
// Copyright 2005, Seagate Technology LLC
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
//
// Revision History
//
// *** Do not edit between "Start Automated RH" and "End Automated RH" ***
// End Automated RH
//
//
//--------------------------------------------------------------------------
/*---------------------------------------------------------------------------
 * Copyright(c) 2005-2006 SMSC
 *
 *  Use of this source code is subject to the terms of the SMSC Software
 *  License Agreement (SLA) under which you licensed this software product.	 
 *  If you did not accept the terms of the SLA, you are not authorized to use
 *  this source code. 
 *  
 *  This code and information is provided as is without warranty of any kind,
 *  either expressed or implied, including but not limited to the implied
 *  warranties of merchantability and/or fitness for a particular purpose.
 *   
 *  File name   : smsc9118.c 
 *  Description : smsc9118 polled driver (non-interrupt driven)
 *  
 *  History	    :
 *  	09-27-06 MDG		First Release
 *			modified for ARM platform
 *----------------------------------------------------------------------------*/

#ifdef CONFIG_DRIVER_SMSC9118

//*************************************************************************
 //  GLOBAL DEFINITIONS

//*************************************************************************
#define 	LAN9118_WARN(s) (printf("%s", s))

#define DRIVER_VERSION          0x100
#define	BUILD_NUMBER			"092706"

//*************************************************************************
 //  DATA STRUCTURE DEFINITIONS

//*************************************************************************


#ifndef 	_SMSC9118_H
#define 	_SMSC9118_H

#ifndef	CONFIG_SMSC9118_BASE
#error	"CONFIG_SMSC9118_BASE is not defined."
#else
#define 	SMSC9118_BASE		CONFIG_SMSC9118_BASE
#endif

#define 	MAC_TIMEOUT 		200
#define 	PHY_TIMEOUT			200
//#define	PHY_AN_TIMEOUT	  3000 * 1000 // 3 seconds
#define 	PHY_AN_TIMEOUT		10	// 3 seconds
#define 	SRST_TIMEOUT		100
#define 	TX_TIMEOUT			3000		// 3000 * 1/HZ
#define 	FFWD_TIMEOUT		100
#define 	PHY_ADDR			1
#define 	FALSE				0
#define 	TRUE				1

#define 	DELAY(n)	( {   \
						int _i = n; \
						do { \
							  ulong _temp; \
							  _temp = *BYTE_TEST; \
						} while (--_i); \
				  } )

struct rxQue {
	  int	index;		// Index into NetRxPackets[]
	  int	len;  		// Length of packet at this index
};

// Lan9118 memory map

// Control/Status Register Map (directly addressable registers)
#define RX_FIFO_PORT				(volatile ulong *)(SMSC9118_BASE + 0x0)
#define RX_FIFO_ALIAS_PORTS 		(volatile ulong *)(SMSC9118_BASE + 0x4)
#define TX_FIFO_PORT				(volatile ulong *)(SMSC9118_BASE + 0x20)
#define TX_FIFO_ALIAS_PORTS 		(volatile ulong *)(SMSC9118_BASE + 0x24)
#define RX_STATUS_FIFO_PORT 		(volatile ulong *)(SMSC9118_BASE + 0x40)
#define RX_STATUS_FIFO_PEEK 		(volatile ulong *)(SMSC9118_BASE + 0x44)
#define TX_STATUS_FIFO_PORT 		(volatile ulong *)(SMSC9118_BASE + 0x48)
#define TX_STATUS_FIFO_PEEK 		(volatile ulong *)(SMSC9118_BASE + 0x4C)
#define TX_STATUS_FIFO_ES 			(0x00008000)
#define TX_STATUS_FIFO_TAG_MSK		(0xffff0000)

#define ID_REV						(volatile ulong *)(SMSC9118_BASE + 0x50)
#define		ID_REV_ID_MASK			(0xFFFF0000)
#define 	ID_REV_CHIP_118   		(0x01180000)
#define 	ID_REV_CHIP_218   		(0x118A0000)
#define 	ID_REV_CHIP_115   		(0x01150000)
#define 	ID_REV_CHIP_215  		(0x115A0000)
#define		ID_REV_REV_MASK			(0x0000FFFF)

#define IRQ_CFG 					(volatile ulong *)(SMSC9118_BASE + 0x54)
#define 	IRQ_CFG_MASTER_INT		(0x00001000)
#define 	IRQ_CFG_ENABLE			(0x00000100)
#define 	IRQ_CFG_IRQ_POL_HIGH	(0x00000010)
#define 	IRQ_CFG_IRQ_TYPE_PUPU	(0x00000001)

#define INT_STS 					(volatile ulong *)(SMSC9118_BASE + 0x58)
#define 	INT_STS_SW_INT			(0x80000000)
#define 	INT_STS_TXSTOP_INT		(0x02000000)
#define 	INT_STS_RXSTOP_INT		(0x01000000)
#define 	INT_STS_RXDFH_INT 		(0x00800000)
#define 	INT_STS_RXDF_INT  		(0x00400000)
#define 	INT_STS_TIOC_INT  		(0x00200000)
#define 	INT_STS_GPT_INT 		(0x00080000)
#define 	INT_STS_PHY_INT 		(0x00040000)
#define 	INT_STS_PMT_INT 		(0x00020000)
#define 	INT_STS_TXSO_INT  		(0x00010000)
#define 	INT_STS_RWT_INT 		(0x00008000)
#define 	INT_STS_RXE_INT 		(0x00004000)
#define 	INT_STS_TXE_INT 		(0x00002000)
#define 	INT_STS_ERX_INT 		(0x00001000)
#define 	INT_STS_TDFU_INT  		(0x00000800)
#define 	INT_STS_TDFO_INT  		(0x00000400)
#define 	INT_STS_TDFA_INT  		(0x00000200)
#define 	INT_STS_TSFF_INT  		(0x00000100)
#define 	INT_STS_TSFL_INT  		(0x00000080)
#define 	INT_STS_RDFO_INT  		(0x00000040)
#define 	INT_STS_RDFL_INT  		(0x00000020)
#define 	INT_STS_RSFF_INT  		(0x00000010)
#define 	INT_STS_RSFL_INT  		(0x00000008)
#define 	INT_STS_GPIO2_INT 		(0x00000004)
#define 	INT_STS_GPIO1_INT 		(0x00000002)
#define 	INT_STS_GPIO0_INT 		(0x00000001)

#define INT_EN						(volatile ulong *)(SMSC9118_BASE + 0x5C)
#define 	INT_EN_SW_INT_EN  		(0x80000000)
#define 	INT_EN_TXSTOP_INT_EN	(0x02000000)
#define 	INT_EN_RXSTOP_INT_EN	(0x01000000)
#define 	INT_EN_RXDFH_INT_EN 	(0x00800000)
#define 	INT_EN_RXDF_INT_EN		(0x00400000)
#define 	INT_EN_TIOC_INT_EN		(0x00200000)
#define 	INT_EN_GPT_INT_EN 		(0x00080000)
#define 	INT_EN_PHY_INT_EN 		(0x00040000)
#define 	INT_EN_PMT_INT_EN 		(0x00020000)
#define 	INT_EN_TXSO_INT_EN		(0x00010000)
#define 	INT_EN_RWT_INT_EN 		(0x00008000)
#define 	INT_EN_RXE_INT_EN 		(0x00004000)
#define 	INT_EN_TXE_INT_EN 		(0x00002000)
#define 	INT_EN_ERX_INT_EN 		(0x00001000)
#define 	INT_EN_TDFU_INT_EN		(0x00000800)
#define 	INT_EN_TDFO_INT_EN		(0x00000400)
#define 	INT_EN_TDFA_INT_EN		(0x00000200)
#define 	INT_EN_TSFF_INT_EN		(0x00000100)
#define 	INT_EN_TSFL_INT_EN		(0x00000080)
#define 	INT_EN_RDFO_INT_EN		(0x00000040)
#define 	INT_EN_RDFL_INT_EN		(0x00000020)
#define 	INT_EN_RSFF_INT_EN		(0x00000010)
#define 	INT_EN_RSFL_INT_EN		(0x00000008)
#define 	INT_EN_GPIO2_EN 		(0x00000004)
#define 	INT_EN_GPIO1_EN 		(0x00000002)
#define 	INT_EN_GPIO0_EN 		(0x00000001)

#define BYTE_TEST		  			(volatile ulong *)(SMSC9118_BASE + 0x64)
#define 	BYTE_TEST_VAL			(0x87654321)

#define FIFO_INT		  			(volatile ulong *)(SMSC9118_BASE + 0x68)
#define 	FIFO_INT_TDAL_MSK 		(0xFF000000)
#define 	FIFO_INT_TSL_MSK  		(0x00FF0000)
#define 	FIFO_INT_RDAL_MSK 		(0x0000FF00)
#define 	FIFO_INT_RSL_MSK  		(0x000000FF)

#define RX_CFG						(volatile ulong *)(SMSC9118_BASE + 0x6C)
#define 	RX_CFG_END_ALIGN4 		(0x00000000)
#define 	RX_CFG_END_ALIGN16		(0x40000000)
#define 	RX_CFG_END_ALIGN32		(0x80000000)
#define 	RX_CFG_FORCE_DISCARD	(0x00008000)
#define 	RX_CFG_RXDOFF_MSK 		(0x00003C00)
#define 	RX_CFG_RXBAD			(0x00000001)

#define TX_CFG						(volatile ulong *)(SMSC9118_BASE + 0x70)
#define 	TX_CFG_TXS_DUMP 		(0x00008000)
#define 	TX_CFG_TXD_DUMP 		(0x00004000)
#define 	TX_CFG_TXSAO			(0x00000004)
#define 	TX_CFG_TX_ON			(0x00000002)
#define 	TX_CFG_STOP_TX			(0x00000001)

#define HW_CFG						(volatile ulong *)(SMSC9118_BASE + 0x74)
#define 	HW_CFG_TTM		  		(0x00200000)
#define 	HW_CFG_SF		  		(0x00100000)
#define 	HW_CFG_TX_FIF_SZ_MSK	(0x000F0000)
#define 	HW_CFG_TR_MSK			(0x00003000)
#define 	HW_CFG_BITMD_MSK  		(0x00000004)
#define 	HW_CFG_BITMD_32 		(0x00000004)
#define 	HW_CFG_SRST_TO			(0x00000002)
#define 	HW_CFG_SRST 	  		(0x00000001)

#define RX_DP_CTL		  			(volatile ulong *)(SMSC9118_BASE + 0x78)
#define 	RX_DP_FFWD		  		(0x80000000)
#define 	RX_DP_RX_FFWD_MSK 		(0x00000FFF)

#define RX_FIFO_INF 	  			(volatile ulong *)(SMSC9118_BASE + 0x7C)
#define 	RX_FIFO_RXSUSED_MSK 	(0x00FF0000)
#define 	RX_FIFO_RXDUSED_MSK 	(0x0000FFFF)

#define TX_FIFO_INF 	  			(volatile ulong *)(SMSC9118_BASE + 0x80)
#define 	TX_FIFO_TXSUSED_MSK 	(0x00FF0000)
#define 	TX_FIFO_TDFREE_MSK		(0x0000FFFF)

#define PWR_MGMT		  			(volatile ulong *)(SMSC9118_BASE + 0x84)
#define 	PWR_MGMT_PM_MODE_MSK	(0x00030000)
#define 	PWR_MGMT_PM_MODE_MSK_LE (0x00000003)
#define 	PWR_MGMT_PM__D0 		(0x00000000)
#define 	PWR_MGMT_PM__D1 		(0x00010000)
#define 	PWR_MGMT_PM__D2 		(0x00020000)
#define 	PWR_MGMT_PHY_RST  		(0x00000400)
#define 	PWR_MGMT_WOL_EN 		(0x00000200)
#define 	PWR_MGMT_ED_EN			(0x00000100)
#define 	PWR_MGMT_PME_TYPE_PUPU	(0x00000040)
#define 	PWR_MGMT_WUPS_MSK 		(0x00000030)
#define 	PWR_MGMT_WUPS_NOWU		(0x00000000)
#define 	PWR_MGMT_WUPS_D2D0		(0x00000010)