dm9ks_ucos.h

硬件设计LPC2138+DM9000AE

#ifndef __DM9KS_H__
#define	__DM9KS_H__
typedef unsigned short u16

//#include "define.h"


/* Board/System/Debug information/definition ---------------- */

#define DM9KS_ID		0x90000A46
#define DM9010_ID		0x90100A46
/*-------register name-----------------------*/
#define DM9KS_NCR		0x00	/* Network control Reg.*/
#define DM9KS_NSR		0x01	/* Network Status Reg.*/
#define DM9KS_TCR		0x02	/* TX control Reg.*/
#define DM9KS_TSRI		0x03
#define DM9KS_TSRII		0x04
#define DM9KS_RXCR		0x05	/* RX control Reg.*/
#define DM9KS_RSR		0x06
#define DM9KS_ROCR		0x07
#define DM9KS_BPTR		0x08
#define DM9KS_FCTR		0x09
#define DM9KS_FCR		0x0a
#define DM9KS_EPCR		0x0b
#define DM9KS_EPAR		0x0c
#define DM9KS_EPDRL		0x0d
#define DM9KS_EPDRH		0x0e
#define DM9KS_WCR		0x0f
#define DM9KS_GPCR		0x1e
#define DM9KS_GPR		0x1f	/* General purpose register */
#define DM9KS_TRPAL		0x22
#define DM9KS_TRPAH		0x23
#define DM9KS_RWPAL		0x24
#define DM9KS_RWPAH		0x25
#define DM9KS_VID_L		0x28
#define DM9KS_VID_H		0x29
#define DM9KS_PID_L		0x2A
#define DM9KS_PID_H		0x2B
#define DM9KS_CHIPR		0x2C
#define DM9KS_TCR2		0x2d
#define DM9KS_OCR		0x2E
#define DM9KS_SMCR		0x2f 	/* Special Mode Control Reg.*/
#define DM9KS_ETXCSR	0x30	/* Early Transmit control/status Reg.*/
#define	DM9KS_TCCR		0x31	/* Checksum cntrol Reg. */
#define DM9KS_RCSR		0x32	/* Receive Checksum status Reg.*/
#define DM9KS_MPAR		0x33
#define DM9KS_LEDCR		0x34
#define DM9KS_BUSCR		0x38
#define DM9KS_INTCR		0x39
#define DM9KS_SCCR		0x50
#define DM9KS_RSCCR		0x51
#define DM9KS_MRCMDX	0xf0
#define DM9KS_MRCMDX1	0xf1
#define DM9KS_MRCMD		0xf2
#define DM9KS_MDRAL		0xf4
#define DM9KS_MDRAH		0xf5
#define DM9KS_MWCMDX	0xf6
#define DM9KS_MWCMD		0xf8
#define DM9KS_MWRL		0xfa
#define DM9KS_MWRH		0xfb
#define DM9KS_TXPLL		0xfc
#define DM9KS_TXPLH		0xfd
#define DM9KS_ISR		0xfe
#define DM9KS_IMR		0xff
/*---------------------------------------------*/
#define DM9KS_REG05		0x30	/* SKIP_CRC/SKIP_LONG */ 
#define DM9KS_REGFF		0x83	/* IMR */
#define DM9KS_DISINTR		0x80

#define DM9KS_PHY		0x40	/* PHY address 0x01 */
#define DM9KS_PKT_RDY		0x01	/* Packet ready to receive */

#define DM9KS_RX_INTR		0x01
#define DM9KS_TX_INTR		0x02
#define DM9KS_LINK_INTR		0x20

#define DM9KS_DWORD_MODE	1
#define DM9KS_BYTE_MODE		2
#define DM9KS_WORD_MODE		0

#define TRUE			1
#define FALSE			0

;enum DM9KS_PHY_mode {
	DM9KS_10MHD   = 0, 
	DM9KS_100MHD  = 1, 
	DM9KS_10MFD   = 4,
	DM9KS_100MFD  = 5, 
	DM9KS_AUTO    = 8
};


#define iobase	0x01200000
#define iodata	0x01200008


int dmfe_open(void);
void dmfe_interrupt(void);
int dmfe_start_xmit(char * pdata, u16 len);

void dmfe_packet_receive(void);




#endif