📄 e1000_main.c
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* active by the system (IFF_UP). At this point all resources needed * for transmit and receive operations are allocated, the interrupt * handler is registered with the OS, the watchdog timer is started, * and the stack is notified that the interface is ready. **/static int e1000_open(struct net_device *netdev){ struct e1000_adapter *adapter = netdev_priv(netdev); int err; /* disallow open during test */ if (test_bit(__E1000_TESTING, &adapter->state)) return -EBUSY; /* allocate transmit descriptors */ err = e1000_setup_all_tx_resources(adapter); if (err) goto err_setup_tx; /* allocate receive descriptors */ err = e1000_setup_all_rx_resources(adapter); if (err) goto err_setup_rx; if (adapter->hw.phy.media_type == e1000_media_type_copper) { e1000_power_up_phy(&adapter->hw); e1000_setup_link(&adapter->hw); }#ifdef NETIF_F_HW_VLAN_TX adapter->mng_vlan_id = E1000_MNG_VLAN_NONE; if ((adapter->hw.mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN)) { e1000_update_mng_vlan(adapter); }#endif /* For 82573 and ICHx if AMT is enabled, let the firmware know * that the network interface is now open */ if (((adapter->hw.mac.type == e1000_82573) || (adapter->hw.mac.type == e1000_ich8lan) || (adapter->hw.mac.type == e1000_ich9lan)) && e1000_check_mng_mode(&adapter->hw)) e1000_get_hw_control(adapter); /* before we allocate an interrupt, we must be ready to handle it. * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt * as soon as we call pci_request_irq, so we have to setup our * clean_rx handler before we do so. */ e1000_configure(adapter); err = e1000_request_irq(adapter); if (err) goto err_req_irq; /* work around PCIe errata with MSI interrupts causing some chipsets to * ignore e1000 MSI messages, which means we need to test our MSI * interrupt now */ err = e1000_test_msi(adapter); if (err) { DPRINTK(PROBE, ERR, "Interrupt allocation failed\n"); goto err_req_irq; } /* From here on the code is the same as e1000_up() */ clear_bit(__E1000_DOWN, &adapter->state); e1000_napi_enable_all(adapter); e1000_irq_enable(adapter); /* fire a link status change interrupt to start the watchdog */ E1000_WRITE_REG(&adapter->hw, E1000_ICS, E1000_ICS_LSC); return E1000_SUCCESS;err_req_irq: e1000_release_hw_control(adapter); /* Power down the PHY so no link is implied when interface is down * * The PHY cannot be powered down if any of the following is TRUE * * (a) WoL is enabled * (b) AMT is active * (c) SoL/IDER session is active */ if (!adapter->wol && adapter->hw.mac.type >= e1000_82540 && adapter->hw.phy.media_type == e1000_media_type_copper) e1000_power_down_phy(&adapter->hw); e1000_free_all_rx_resources(adapter);err_setup_rx: e1000_free_all_tx_resources(adapter);err_setup_tx: e1000_reset(adapter); return err;}/** * e1000_close - Disables a network interface * @netdev: network interface device structure * * Returns 0, this is not allowed to fail * * The close entry point is called when an interface is de-activated * by the OS. The hardware is still under the drivers control, but * needs to be disabled. A global MAC reset is issued to stop the * hardware, and all transmit and receive resources are freed. **/static int e1000_close(struct net_device *netdev){ struct e1000_adapter *adapter = netdev_priv(netdev); WARN_ON(test_bit(__E1000_RESETTING, &adapter->state)); e1000_down(adapter); /* Power down the PHY so no link is implied when interface is down * * The PHY cannot be powered down if any of the following is TRUE * * (a) WoL is enabled * (b) AMT is active * (c) SoL/IDER session is active */ if (!adapter->wol && adapter->hw.mac.type >= e1000_82540 && adapter->hw.phy.media_type == e1000_media_type_copper) e1000_power_down_phy(&adapter->hw); e1000_free_irq(adapter); e1000_free_all_tx_resources(adapter); e1000_free_all_rx_resources(adapter);#ifdef NETIF_F_HW_VLAN_TX /* kill manageability vlan ID if supported, but not if a vlan with * the same ID is registered on the host OS (let 8021q kill it) */ if ((adapter->hw.mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN) && !(adapter->vlgrp && vlan_group_get_device(adapter->vlgrp, adapter->mng_vlan_id))) { e1000_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id); }#endif /* For 82573 and ICHx if AMT is enabled, let the firmware know * that the network interface is now closed */ if (((adapter->hw.mac.type == e1000_82573) || (adapter->hw.mac.type == e1000_ich8lan) || (adapter->hw.mac.type == e1000_ich9lan)) && e1000_check_mng_mode(&adapter->hw)) e1000_release_hw_control(adapter); return 0;}/** * e1000_check_64k_bound - check that memory doesn't cross 64kB boundary * @adapter: address of board private structure * @start: address of beginning of memory * @len: length of memory **/static bool e1000_check_64k_bound(struct e1000_adapter *adapter, void *start, unsigned long len){ unsigned long begin = (unsigned long) start; unsigned long end = begin + len; /* First rev 82545 and 82546 need to not allow any memory * write location to cross 64k boundary due to errata 23 */ if (adapter->hw.mac.type == e1000_82545 || adapter->hw.mac.type == e1000_82546) { return ((begin ^ (end - 1)) >> 16) != 0 ? FALSE : TRUE; } return TRUE;}/** * e1000_setup_tx_resources - allocate Tx resources (Descriptors) * @adapter: board private structure * @tx_ring: tx descriptor ring (for a specific queue) to setup * * Return 0 on success, negative on failure **/static int e1000_setup_tx_resources(struct e1000_adapter *adapter, struct e1000_tx_ring *tx_ring){ struct pci_dev *pdev = adapter->pdev; int size; size = sizeof(struct e1000_buffer) * tx_ring->count; tx_ring->buffer_info = vmalloc(size); if (!tx_ring->buffer_info) { DPRINTK(PROBE, ERR, "Unable to allocate memory for the transmit descriptor ring\n"); return -ENOMEM; } memset(tx_ring->buffer_info, 0, size); /* round up to nearest 4K */ tx_ring->size = tx_ring->count * sizeof(struct e1000_tx_desc); tx_ring->size = ALIGN(tx_ring->size, 4096); tx_ring->desc = pci_alloc_consistent(pdev, tx_ring->size, &tx_ring->dma); if (!tx_ring->desc) {setup_tx_desc_die: vfree(tx_ring->buffer_info); DPRINTK(PROBE, ERR, "Unable to allocate memory for the transmit descriptor ring\n"); return -ENOMEM; } /* Fix for errata 23, can't cross 64kB boundary */ if (!e1000_check_64k_bound(adapter, tx_ring->desc, tx_ring->size)) { void *olddesc = tx_ring->desc; dma_addr_t olddma = tx_ring->dma; DPRINTK(TX_ERR, ERR, "tx_ring align check failed: %u bytes " "at %p\n", tx_ring->size, tx_ring->desc); /* Try again, without freeing the previous */ tx_ring->desc = pci_alloc_consistent(pdev, tx_ring->size, &tx_ring->dma); /* Failed allocation, critical failure */ if (!tx_ring->desc) { pci_free_consistent(pdev, tx_ring->size, olddesc, olddma); goto setup_tx_desc_die; } if (!e1000_check_64k_bound(adapter, tx_ring->desc, tx_ring->size)) { /* give up */ pci_free_consistent(pdev, tx_ring->size, tx_ring->desc, tx_ring->dma); pci_free_consistent(pdev, tx_ring->size, olddesc, olddma); DPRINTK(PROBE, ERR, "Unable to allocate aligned memory " "for the transmit descriptor ring\n"); vfree(tx_ring->buffer_info); return -ENOMEM; } else { /* Free old allocation, new allocation was successful */ pci_free_consistent(pdev, tx_ring->size, olddesc, olddma); } } memset(tx_ring->desc, 0, tx_ring->size); tx_ring->next_to_use = 0; tx_ring->next_to_clean = 0; spin_lock_init(&tx_ring->tx_lock); return 0;}/** * e1000_setup_all_tx_resources - wrapper to allocate Tx resources * @adapter: board private structure * * this allocates tx resources for all queues, return 0 on success, negative * on failure **/int e1000_setup_all_tx_resources(struct e1000_adapter *adapter){ int i, err = 0; for (i = 0; i < adapter->num_tx_queues; i++) { err = e1000_setup_tx_resources(adapter, &adapter->tx_ring[i]); if (err) { DPRINTK(PROBE, ERR, "Allocation for Tx Queue %u failed\n", i); for (i-- ; i >= 0; i--) e1000_free_tx_resources(adapter, &adapter->tx_ring[i]); break; } } return err;}/** * e1000_configure_tx - Configure 8254x Transmit Unit after Reset * @adapter: board private structure * * Configure the Tx unit of the MAC after a reset. **/static void e1000_configure_tx(struct e1000_adapter *adapter){ u64 tdba; struct e1000_hw *hw = &adapter->hw; u32 tdlen, tctl, tipg, tarc; u32 ipgr1, ipgr2; int i; /* Setup the HW Tx Head and Tail descriptor pointers */ for (i = 0; i < adapter->num_tx_queues; i++) { tdba = adapter->tx_ring[i].dma; tdlen = adapter->tx_ring[i].count * sizeof(struct e1000_tx_desc); E1000_WRITE_REG(hw, E1000_TDBAL(i), (tdba & 0x00000000ffffffffULL)); E1000_WRITE_REG(hw, E1000_TDBAH(i), (tdba >> 32)); E1000_WRITE_REG(hw, E1000_TDLEN(i), tdlen); E1000_WRITE_REG(hw, E1000_TDH(i), 0); E1000_WRITE_REG(hw, E1000_TDT(i), 0); adapter->tx_ring[i].tdh = E1000_REGISTER(hw, E1000_TDH(i)); adapter->tx_ring[i].tdt = E1000_REGISTER(hw, E1000_TDT(i)); } /* Set the default values for the Tx Inter Packet Gap timer */ if (adapter->hw.mac.type <= e1000_82547_rev_2 && (hw->phy.media_type == e1000_media_type_fiber || hw->phy.media_type == e1000_media_type_internal_serdes)) tipg = DEFAULT_82543_TIPG_IPGT_FIBER; else tipg = DEFAULT_82543_TIPG_IPGT_COPPER; switch (hw->mac.type) { case e1000_82542: tipg = DEFAULT_82542_TIPG_IPGT; ipgr1 = DEFAULT_82542_TIPG_IPGR1; ipgr2 = DEFAULT_82542_TIPG_IPGR2; break; case e1000_80003es2lan: ipgr1 = DEFAULT_82543_TIPG_IPGR1; ipgr2 = DEFAULT_80003ES2LAN_TIPG_IPGR2; break; default: ipgr1 = DEFAULT_82543_TIPG_IPGR1; ipgr2 = DEFAULT_82543_TIPG_IPGR2; break; } tipg |= ipgr1 << E1000_TIPG_IPGR1_SHIFT; tipg |= ipgr2 << E1000_TIPG_IPGR2_SHIFT; E1000_WRITE_REG(hw, E1000_TIPG, tipg); /* Set the Tx Interrupt Delay register */ E1000_WRITE_REG(hw, E1000_TIDV, adapter->tx_int_delay); if (adapter->flags & E1000_FLAG_HAS_INTR_MODERATION) E1000_WRITE_REG(hw, E1000_TADV, adapter->tx_abs_int_delay); /* Program the Transmit Control Register */ tctl = E1000_READ_REG(hw, E1000_TCTL); tctl &= ~E1000_TCTL_CT; tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC | (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT); if (hw->mac.type == e1000_82571 || hw->mac.type == e1000_82572) { tarc = E1000_READ_REG(hw, E1000_TARC(0)); /* set the speed mode bit, we'll clear it if we're not at * gigabit link later */#define SPEED_MODE_BIT (1 << 21) tarc |= SPEED_MODE_BIT; E1000_WRITE_REG(hw, E1000_TARC(0), tarc); } else if (hw->mac.type == e1000_80003es2lan) { tarc = E1000_READ_REG(hw, E1000_TARC(0)); tarc |= 1; E1000_WRITE_REG(hw, E1000_TARC(0), tarc); tarc = E1000_READ_REG(hw, E1000_TARC(1)); tarc |= 1; E1000_WRITE_REG(hw, E1000_TARC(1), tarc); } e1000_config_collision_dist(hw); /* Setup Transmit Descriptor Settings for eop descriptor */ adapter->txd_cmd = E1000_TXD_CMD_EOP | E1000_TXD_CMD_IFCS; /* only set IDE if we are delaying interrupts using the timers */ if (adapter->tx_int_delay) adapter->txd_cmd |= E1000_TXD_CMD_IDE; if (hw->mac.type < e1000_82543) adapter->txd_cmd |= E1000_TXD_CMD_RPS; else adapter->txd_cmd |= E1000_TXD_CMD_RS; /* Cache if we're 82544 running in PCI-X because we'll * need this to apply a workaround later in the send path. */ if (hw->mac.type == e1000_82544 && hw->bus.type == e1000_bus_type_pcix) adapter->pcix_82544 = 1; E1000_WRITE_REG(hw, E1000_TCTL, tctl);}/** * e1000_setup_rx_resources - allocate Rx resources (Descriptors) * @adapter: board private structure * @rx_ring: rx descriptor ring (for a specific queue) to setup * * Returns 0 on success, negative on failure **/static int e1000_setup_rx_resources(struct e1000_adapter *adapter, struct e1000_rx_ring *rx_ring){ struct pci_dev *pdev = adapter->pdev; int size, desc_len; size = sizeof(struct e1000_rx_buffer) * rx_ring->count; rx_ring->buffer_info = vmalloc(size); if (!rx_ring->buffer_info) { DPRINTK(PROBE, ERR, "Unable to allocate memory for the receive descriptor ring\n"); return -ENOMEM; } memset(rx_ring->buffer_info, 0, size); rx_ring->ps_page = kcalloc(rx_ring->count, sizeof(struct e1000_ps_page), GFP_KERNEL); if (!rx_ring->ps_page) { vfree(rx_ring->buffer_info); DPRINTK(PROBE, ERR, "Unable to allocate memory for the receive descriptor ring\n"); return -ENOMEM; } rx_ring->ps_page_dma = kcalloc(rx_ring->count,
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