main.lst

本程序为编码器调节电压,能校对:输出电压,输入电压,与校对调节输出的电压值,适合做通用数字电源程序

 659               	.LM79:
 660               	/* prologue: frame size=0 */
 661               	/* prologue end (size=0) */
 129:main.c        **** static uch  x,y;
 130:main.c        **** if(x>10){
 663               	.LM80:
 664 0206 8091 0000 		lds r24,x.0
 665 020a 8B30      		cpi r24,lo8(11)
 666 020c 58F1      		brlo .L77
 131:main.c        **** x=0;
 668               	.LM81:
 669 020e 1092 0000 		sts x.0,__zero_reg__
 132:main.c        **** 	if(y<10){
 671               	.LM82:
 672 0212 2091 0000 		lds r18,y.1
 673 0216 2A30      		cpi r18,lo8(10)
 674 0218 10F5      		brsh .L78
 133:main.c        **** 	vo_a[y]=adc_1;
 676               	.LM83:
 677 021a E22F      		mov r30,r18
 678 021c FF27      		clr r31
 679 021e EE0F      		add r30,r30
 680 0220 FF1F      		adc r31,r31
 681 0222 DF01      		movw r26,r30
 682 0224 A050      		subi r26,lo8(-(vo_a))
 683 0226 B040      		sbci r27,hi8(-(vo_a))
 684 0228 8091 0000 		lds r24,adc_1
 685 022c 9091 0000 		lds r25,(adc_1)+1
 686 0230 8D93      		st X+,r24
 687 0232 9C93      		st X,r25
 134:main.c        **** 	vi_a[y]=adc_2;
 689               	.LM84:
 690 0234 DF01      		movw r26,r30
 691 0236 A050      		subi r26,lo8(-(vi_a))
 692 0238 B040      		sbci r27,hi8(-(vi_a))
 693 023a 8091 0000 		lds r24,adc_2
 694 023e 9091 0000 		lds r25,(adc_2)+1
 695 0242 8D93      		st X+,r24
 696 0244 9C93      		st X,r25
 135:main.c        **** 	va_a[y]=adc_3;
 698               	.LM85:
 699 0246 E050      		subi r30,lo8(-(va_a))
 700 0248 F040      		sbci r31,hi8(-(va_a))
 701 024a 8091 0000 		lds r24,adc_3
 702 024e 9091 0000 		lds r25,(adc_3)+1
 703 0252 9183      		std Z+1,r25
 704 0254 8083      		st Z,r24
 136:main.c        **** 	 y++;
 706               	.LM86:
 707 0256 2F5F      		subi r18,lo8(-(1))
 708 0258 2093 0000 		sts y.1,r18
 709 025c 06C0      		rjmp .L80
 710               	.L78:
 137:main.c        **** 	 }
 138:main.c        **** 	 else y=0;
 712               	.LM87:
 713 025e 1092 0000 		sts y.1,__zero_reg__
 714 0262 03C0      		rjmp .L80
 715               	.L77:
 139:main.c        **** 	 }
 140:main.c        **** 	 else x++;
 717               	.LM88:
 718 0264 8F5F      		subi r24,lo8(-(1))
 719 0266 8093 0000 		sts x.0,r24
 720               	.L80:
 141:main.c        **** if(y==10){
 722               	.LM89:
 723 026a 8091 0000 		lds r24,y.1
 724 026e 8A30      		cpi r24,lo8(10)
 725 0270 E9F4      		brne .L76
 142:main.c        **** 	vo2=adc_maxmin(vo_a,1);
 727               	.LM90:
 728 0272 61E0      		ldi r22,lo8(1)
 729 0274 80E0      		ldi r24,lo8(vo_a)
 730 0276 90E0      		ldi r25,hi8(vo_a)
 731 0278 0E94 0000 		call adc_maxmin
 732 027c 9093 0000 		sts (vo2)+1,r25
 733 0280 8093 0000 		sts vo2,r24
 143:main.c        **** 	vi2=adc_maxmin(vi_a,2);
 735               	.LM91:
 736 0284 62E0      		ldi r22,lo8(2)
 737 0286 80E0      		ldi r24,lo8(vi_a)
 738 0288 90E0      		ldi r25,hi8(vi_a)
 739 028a 0E94 0000 		call adc_maxmin
 740 028e 9093 0000 		sts (vi2)+1,r25
 741 0292 8093 0000 		sts vi2,r24
 144:main.c        **** 	va2=adc_maxmin(va_a,3);
 743               	.LM92:
 744 0296 63E0      		ldi r22,lo8(3)
 745 0298 80E0      		ldi r24,lo8(va_a)
 746 029a 90E0      		ldi r25,hi8(va_a)
 747 029c 0E94 0000 		call adc_maxmin
 748 02a0 9093 0000 		sts (va2)+1,r25
 749 02a4 8093 0000 		sts va2,r24
 145:main.c        ****     y=0;
 751               	.LM93:
 752 02a8 1092 0000 		sts y.1,__zero_reg__
 753               	.L76:
 754 02ac 0895      		ret
 755               	/* epilogue: frame size=0 */
 756               	/* epilogue: noreturn */
 757               	/* epilogue end (size=0) */
 758               	/* function adc_sy size 84 (84) */
 764               	.Lscope9:
 766               	.global	__vector_14
 768               	__vector_14:
 146:main.c        **** } 
 147:main.c        **** 	 }
 148:main.c        **** 
 149:main.c        **** SIGNAL(SIG_ADC)
 150:main.c        **** {
 770               	.LM94:
 771               	/* prologue: frame size=0 */
 772 02ae 1F92      		push __zero_reg__
 773 02b0 0F92      		push __tmp_reg__
 774 02b2 0FB6      		in __tmp_reg__,__SREG__
 775 02b4 0F92      		push __tmp_reg__
 776 02b6 1124      		clr __zero_reg__
 777 02b8 8F93      		push r24
 778 02ba 9F93      		push r25
 779               	/* prologue end (size=7) */
 151:main.c        **** if(ADMUX==0xC0){ADMUX=0xC1;adc_1=ADC;return;}
 781               	.LM95:
 782 02bc 87B1      		in r24,39-0x20
 783 02be 803C      		cpi r24,lo8(-64)
 784 02c0 49F4      		brne .L83
 786               	.LM96:
 787 02c2 81EC      		ldi r24,lo8(-63)
 788 02c4 87B9      		out 39-0x20,r24
 789 02c6 84B1      		in r24,36-0x20
 790 02c8 95B1      		in r25,(36)+1-0x20
 791 02ca 9093 0000 		sts (adc_1)+1,r25
 792 02ce 8093 0000 		sts adc_1,r24
 793 02d2 0BC0      		rjmp .L82
 794               	.L83:
 152:main.c        **** if(ADMUX==0xC1){ADMUX=0xC0;adc_2=ADC;return;}
 796               	.LM97:
 797 02d4 87B1      		in r24,39-0x20
 798 02d6 813C      		cpi r24,lo8(-63)
 799 02d8 41F4      		brne .L82
 800 02da 80EC      		ldi r24,lo8(-64)
 801 02dc 87B9      		out 39-0x20,r24
 802 02de 84B1      		in r24,36-0x20
 803 02e0 95B1      		in r25,(36)+1-0x20
 804 02e2 9093 0000 		sts (adc_2)+1,r25
 805 02e6 8093 0000 		sts adc_2,r24
 806               	.L82:
 807               	/* epilogue: frame size=0 */
 808 02ea 9F91      		pop r25
 809 02ec 8F91      		pop r24
 810 02ee 0F90      		pop __tmp_reg__
 811 02f0 0FBE      		out __SREG__,__tmp_reg__
 812 02f2 0F90      		pop __tmp_reg__
 813 02f4 1F90      		pop __zero_reg__
 814 02f6 1895      		reti
 815               	/* epilogue end (size=7) */
 816               	/* function __vector_14 size 37 (23) */
 818               	.Lscope10:
 820               	.global	__vector_9
 822               	__vector_9:
 153:main.c        **** //if(ADMUX==0xC2){ADMUX=0xC0;adc_3=ADC;return;}
 154:main.c        **** }
 155:main.c        **** SIGNAL(SIG_OVERFLOW0) 
 156:main.c        **** {
 824               	.LM98:
 825               	/* prologue: frame size=0 */
 826 02f8 1F92      		push __zero_reg__
 827 02fa 0F92      		push __tmp_reg__
 828 02fc 0FB6      		in __tmp_reg__,__SREG__
 829 02fe 0F92      		push __tmp_reg__
 830 0300 1124      		clr __zero_reg__
 831 0302 2F93      		push r18
 832 0304 3F93      		push r19
 833 0306 4F93      		push r20
 834 0308 5F93      		push r21
 835 030a 6F93      		push r22
 836 030c 7F93      		push r23
 837 030e 8F93      		push r24
 838 0310 9F93      		push r25
 839 0312 AF93      		push r26
 840 0314 BF93      		push r27
 841 0316 EF93      		push r30
 842 0318 FF93      		push r31
 843               	/* prologue end (size=17) */
 157:main.c        **** 
 158:main.c        ****  ADCSRA|=_BV(ADSC);
 845               	.LM99:
 846 031a 369A      		sbi 38-0x20,6
 159:main.c        ****  uch tep;
 160:main.c        ****  tep=key_in&0xc0;
 848               	.LM100:
 849 031c 99B3      		in r25,57-0x20
 850 031e 9095      		com r25
 851 0320 907C      		andi r25,lo8(-64)
 161:main.c        ****  ks2=tep;
 853               	.LM101:
 854 0322 9093 0000 		sts ks2,r25
 162:main.c        ****  xiao=tep;
 856               	.LM102:
 857 0326 9093 0000 		sts xiao,r25
 163:main.c        **** if(tep){
 859               	.LM103:
 860 032a 9923      		tst r25
 861 032c 59F0      		breq .L86
 164:main.c        **** 	if(ks==10){tep2=tep;ks++;}
 863               	.LM104:
 864 032e 8091 0000 		lds r24,ks
 865 0332 282F      		mov r18,r24
 866 0334 2F5F      		subi r18,lo8(-(1))
 867 0336 8A30      		cpi r24,lo8(10)
 868 0338 11F4      		brne .L87
 869 033a 9093 0000 		sts tep2,r25
 870               	.L87:
 165:main.c        **** 	 else ks++;
 872               	.LM105:
 873 033e 2093 0000 		sts ks,r18
 874 0342 0DC0      		rjmp .L89
 875               	.L86:
 166:main.c        **** 	}
 167:main.c        **** else{ks=0;if(tep2){key=tep2;make=1;}tep2=0;}
 877               	.LM106:
 878 0344 9093 0000 		sts ks,r25
 879 0348 8091 0000 		lds r24,tep2
 880 034c 8823      		tst r24
 881 034e 29F0      		breq .L90
 882 0350 8093 0000 		sts key,r24
 883 0354 81E0      		ldi r24,lo8(1)
 884 0356 8093 0000 		sts make,r24
 885               	.L90:
 886 035a 9093 0000 		sts tep2,r25
 887               	.L89:
 168:main.c        **** 
 169:main.c        ****   if(ch_s){
 889               	.LM107:
 890 035e 8091 0000 		lds r24,ch_s
 891 0362 8823      		tst r24
 892 0364 F9F0      		breq .L91
 170:main.c        ****               w_by(*ch_sp);ch_s=0;
 894               	.LM108:
 895 0366 E091 0000 		lds r30,ch_sp
 896 036a F091 0000 		lds r31,(ch_sp)+1
 897 036e 8081      		ld r24,Z
 898 0370 0E94 0000 		call w_by
 899 0374 1092 0000 		sts ch_s,__zero_reg__
 171:main.c        ****               if(ch_x<15){ch_x++;ch_sp++;}
 901               	.LM109:
 902 0378 8091 0000 		lds r24,ch_x
 903 037c 8F30      		cpi r24,lo8(15)
 904 037e 48F4      		brsh .L92
 905 0380 8F5F      		subi r24,lo8(-(1))
 906 0382 8093 0000 		sts ch_x,r24
 907 0386 8091 0000 		lds r24,ch_sp
 908 038a 9091 0000 		lds r25,(ch_sp)+1
 909 038e 0196      		adiw r24,1
 910 0390 04C0      		rjmp .L101
 911               	.L92:
 172:main.c        ****                else {ch_x=0;ch_sp=&xy_ch;}
 913               	.LM110:
 914 0392 1092 0000 		sts ch_x,__zero_reg__
 915 0396 80E0      		ldi r24,lo8(xy_ch)
 916 0398 90E0      		ldi r25,hi8(xy_ch)
 917               	.L101:
 918 039a 9093 0000 		sts (ch_sp)+1,r25
 919 039e 8093 0000 		sts ch_sp,r24
 920 03a2 07C0      		rjmp .L94
 921               	.L91:
 173:main.c        ****             }
 174:main.c        **** else {xini(ch_x);ch_s=1;}
 923               	.LM111:
 924 03a4 8091 0000 		lds r24,ch_x
 925 03a8 0E94 0000 		call xini
 926 03ac 81E0      		ldi r24,lo8(1)
 927 03ae 8093 0000 		sts ch_s,r24
 928               	.L94:
 175:main.c        **** 
 176:main.c        ****  if(di1){DIL;di1--;}//第一次响
 930               	.LM112:
 931 03b2 8091 0000 		lds r24,di1
 932 03b6 8823      		tst r24
 933 03b8 29F0      		breq .L95
 934 03ba 9798      		cbi 50-0x20,7
 935 03bc 8150      		subi r24,lo8(-(-1))
 936 03be 8093 0000 		sts di1,r24
 937 03c2 12C0      		rjmp .L96
 938               	.L95:
 177:main.c        ****   else {
 178:main.c        ****     if(di2){di2--;DIH;}//第二次延时
 940               	.LM113:
 941 03c4 8091 0000 		lds r24,di2
 942 03c8 8823      		tst r24
 943 03ca 21F0      		breq .L97
 944 03cc 8150      		subi r24,lo8(-(-1))
 945 03ce 8093 0000 		sts di2,r24
 946 03d2 09C0      		rjmp .L99
 947               	.L97:
 179:main.c        **** 	  else {if(di3){di3--;DIL;}else DIH;}//第三次响
 949               	.LM114:
 950 03d4 8091 0000 		lds r24,di3
 951 03d8 8823      		tst r24
 952 03da 29F0      		breq .L99
 953 03dc 8150      		subi r24,lo8(-(-1))
 954 03de 8093 0000 		sts di3,r24
 955 03e2 9798      		cbi 50-0x20,7
 956 03e4 01C0      		rjmp .L96
 957               	.L99:
 958 03e6 979A      		sbi 50-0x20,7
 959               	.L96:
 180:main.c        **** 	  }
 181:main.c        ****  TCNT0=250;//20MS
 961               	.LM115:
 962 03e8 8AEF      		ldi r24,lo8(-6)
 963 03ea 82BF      		out 82-0x20,r24
 964               	/* epilogue: frame size=0 */
 965 03ec FF91      		pop r31
 966 03ee EF91      		pop r30
 967 03f0 BF91      		pop r27
 968 03f2 AF91      		pop r26
 969 03f4 9F91      		pop r25
 970 03f6 8F91      		pop r24
 971 03f8 7F91      		pop r23
 972 03fa 6F91      		pop r22
 973 03fc 5F91      		pop r21
 974 03fe 4F91      		pop r20
 975 0400 3F91      		pop r19
 976 0402 2F91      		pop r18
 977 0404 0F90      		pop __tmp_reg__
 978 0406 0FBE      		out __SREG__,__tmp_reg__
 979 0408 0F90      		pop __tmp_reg__
 980 040a 1F90      		pop __zero_reg__
 981 040c 1895      		reti
 982               	/* epilogue end (size=17) */
 983               	/* function __vector_9 size 139 (105) */
 988               	.Lscope11:
 990               	.global	__vector_1
 992               	__vector_1:
 182:main.c        ****   // power++;
 183:main.c        **** }
 184:main.c        **** uch s_up;
 185:main.c        **** uch s_down;
 186:main.c        **** SIGNAL(SIG_INTERRUPT0){
 994               	.LM116:
 995               	/* prologue: frame size=0 */
 996 040e 1F92      		push __zero_reg__
 997 0410 0F92      		push __tmp_reg__
 998 0412 0FB6      		in __tmp_reg__,__SREG__
 999 0414 0F92      		push __tmp_reg__
 1000 0416 1124      		clr __zero_reg__
 1001 0418 2F93      		push r18