f2812_sysctrl.c

TMS320F2812串行口通信程序－采用循环缓冲区方式

#include "F2812_DevEmu.h"

#include "F2812_SysCtrl.h"


void SysCtrlInit(void)
{
	volatile Uint16 i;					// General purpose Uint16
	volatile int16 dummy;					// General purpose volatile int16

    asm(" 	EALLOW	");
	
	DevEmuRegs.PROTSTART = 0x0100;		// Write default value to protection start register
	DevEmuRegs.PROTRANGE = 0x00FF;		// Write default value to protection range register
	DevEmuRegs.M0RAMDFT = 0x0300;
    DevEmuRegs.M1RAMDFT = 0x0300;
    DevEmuRegs.L0RAMDFT = 0x0300;
    DevEmuRegs.L1RAMDFT = 0x0300;
    DevEmuRegs.H0RAMDFT = 0x0300;   
	dummy = CsmPwl.PSWD0;				// Dummy read of PWL locations
	dummy = CsmPwl.PSWD1;				// Dummy read of PWL locations
	dummy = CsmPwl.PSWD2;				// Dummy read of PWL locations
	dummy = CsmPwl.PSWD3;				// Dummy read of PWL locations
	dummy = CsmPwl.PSWD4;				// Dummy read of PWL locations
	dummy = CsmPwl.PSWD5;				// Dummy read of PWL locations
	dummy = CsmPwl.PSWD6;				// Dummy read of PWL locations
	dummy = CsmPwl.PSWD7;				// Dummy read of PWL locations
	//  System CLK configuration
 	SysCtrlRegs.WDCR = 0x00E8;			// WDPS[2..0]=000b,WDCHK[2..0]=101b,WDDIS=1,WDFLAG=0
	SysCtrlRegs.PLLCR = 10;				// CLKIN = OSCCLK*10/2
   	for(i= 0; i< 5000; i++){}			// Wait for PLL Stable about 131072 CLKIN
    for(i=0; i<510; i++)
	{
		asm(" RPT #255 || NOP");		// 257 cycles,The operation won't be interruptable. 
		SysCtrlRegs.WDKEY = 0x0055;		// Service the watchdog while waiting
		SysCtrlRegs.WDKEY = 0x00AA;		// in case the user enabled it.
	}  

	//  HISPCP/LOSPCP prescale register settings, normally it will be set to default values
    SysCtrlRegs.HISPCP.all = 0x0000;	// HSPCLK=SYSCLKOUT
    SysCtrlRegs.LOSPCP.all = 0x0002;	// LSPCLK=SYSCLKOUT/4
   	
	//  Peripheral clock enables set for the selected peripherals.   
    SysCtrlRegs.PCLKCR.bit.EVAENCLK=0;	// EV-A CLK
    SysCtrlRegs.PCLKCR.bit.EVBENCLK=0;	// EV-B CLK
   
    SysCtrlRegs.PCLKCR.bit.ADCENCLK=0;	// ADC CLK
	SysCtrlRegs.PCLKCR.bit.SPIENCLK=0;	// SPICLK

    SysCtrlRegs.PCLKCR.bit.SCIENCLKA=1;	// SCI-A CLK
    SysCtrlRegs.PCLKCR.bit.SCIENCLKB=1;	// SCI-B CLK
       
    SysCtrlRegs.PCLKCR.bit.MCBSPENCLK=0; //McBSP CLK
    SysCtrlRegs.PCLKCR.bit.ECANENCLK=0;	 //eCAN CLK
				
    asm("	EDIS	");
	
}

//---------------------------------------------------------------------------
// KickDog: 
//---------------------------------------------------------------------------
// This function resets the watchdog timer.
// Enable this function for using KickDog in the application 
 
void KickDog(void)
{
    asm("	EALLOW	");
    SysCtrlRegs.WDKEY = 0x0055;
    SysCtrlRegs.WDKEY = 0x00AA;
    asm("	EDIS	");
}
	
#pragma CODE_SECTION(InitFlash, "secureRamFuncs")
void InitFlash(void)
{
	asm(" EALLOW");									// Enable EALLOW protected register access
	FlashRegs.FPWR.bit.PWR = 3;						// Pump and bank set to active mode
	FlashRegs.FSTATUS.bit.V3STAT = 1;				// Clear the 3VSTAT bit
	FlashRegs.FSTDBYWAIT.bit.STDBYWAIT = 0x01FF;	// Sleep to standby transition cycles
	FlashRegs.FACTIVEWAIT.bit.ACTIVEWAIT = 0x01FF;	// Standby to active transition cycles
	FlashRegs.FBANKWAIT.bit.RANDWAIT = 5;			// Random access waitstates
	FlashRegs.FBANKWAIT.bit.PAGEWAIT = 5;			// Paged access waitstates
	FlashRegs.FOTPWAIT.bit.OPTWAIT=8;			// OTP waitstates
	FlashRegs.FOPT.bit.ENPIPE = 1;					// Enable the flash pipeline
	asm(" EDIS");									// Disable EALLOW protected register access

/*** Force a complete pipeline flush to ensure that the write to the last register
     configured occurs before returning.  Safest thing is to wait 8 full cycles. ***/

    asm(" RPT #6 || NOP");

} //end of InitFlash()

/*** end of file *****************************************************/