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📄 jiaotongdengkongzhi.rpt

📁 课程设计《交通灯控制的设计》
💻 RPT
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Total input pins required:                       3
Total input I/O cell registers required:         0
Total output pins required:                     16
Total output I/O cell registers required:        0
Total buried I/O cell registers required:        0
Total bidirectional pins required:               0
Total reserved pins required                     0
Total logic cells required:                    427
Total flipflops required:                       41
Total packed registers required:                 0
Total logic cells in carry chains:               0
Total number of carry chains:                    0
Total logic cells in cascade chains:             0
Total number of cascade chains:                  0
Total single-pin Clock Enables required:         0
Total single-pin Output Enables required:        0

Synthesized logic cells:                       113/1152   (  9%)

Logic Cell and Embedded Cell Counts

Column:  01  02  03  04  05  06  07  08  09  10  11  12  EA  13  14  15  16  17  18  19  20  21  22  23  24  Total(LC/EC)
 A:      8   8   8   7   8   7   8   8   8   8   6   8   0   3   8   8   7   6   8   8   1   7   8   8   8    172/0  
 B:      8   0   0   0   0   4   0   0   0   0   0   8   0   0   0   0   0   0   0   0   0   0   0   0   0     20/0  
 C:      0   0   0   0   0   0   0   0   2   0   0   0   0   0   8   0   0   8   2   0   0   2   8   8   0     38/0  
 D:      0   0   1   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   8   0   8   0   0     17/0  
 E:      8   8   2   8   8   8   8   8   8   8   8   8   0   8   8   1   8   8   8   8   7   8   8   8   8    178/0  
 F:      0   0   0   0   0   1   0   0   0   0   0   0   0   0   1   0   0   0   0   0   0   0   0   0   0      2/0  

Total:  24  16  11  15  16  20  16  16  18  16  14  24   0  11  25   9  15  22  18  16  16  17  32  24  16    427/0  



Device-Specific Information:     d:\我的文档\zyl\37\s8\jiaotongdengkongzhi.rpt
jiaotongdengkongzhi

** INPUTS **

                                                    Fan-In    Fan-Out
 Pin     LC     EC   Row  Col  Primitive    Code      INP  FBK  OUT  FBK  Name
  23      -     -    D    --      INPUT                0    0    0   28  clk
  26      -     -    E    --      INPUT                0    0    0   13  disclk
   7      -     -    A    --      INPUT                0    0    0    9  sb


Code:

s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable


Device-Specific Information:     d:\我的文档\zyl\37\s8\jiaotongdengkongzhi.rpt
jiaotongdengkongzhi

** OUTPUTS **

       Fed By Fed By                                Fan-In    Fan-Out
 Pin     LC     EC   Row  Col  Primitive    Code      INP  FBK  OUT  FBK  Name
  36      -     -    -    24     OUTPUT                0    1    0    0  bg
  38      -     -    -    22     OUTPUT                0    1    0    0  br
  37      -     -    -    23     OUTPUT                0    1    0    0  by
  90      -     -    C    --     OUTPUT                0    1    0    0  led0
  91      -     -    C    --     OUTPUT                0    1    0    0  led1
  92      -     -    C    --     OUTPUT                0    1    0    0  led2
  95      -     -    B    --     OUTPUT                0    1    0    0  led3
  96      -     -    B    --     OUTPUT                0    1    0    0  led4
  97      -     -    B    --     OUTPUT                0    1    0    0  led5
  98      -     -    B    --     OUTPUT                0    1    0    0  led6
  31      -     -    F    --     OUTPUT                0    1    0    0  mg
  33      -     -    F    --     OUTPUT                0    1    0    0  mr
  32      -     -    F    --     OUTPUT                0    1    0    0  my
  20      -     -    D    --     OUTPUT                0    1    0    0  sel0
  21      -     -    D    --     OUTPUT                0    1    0    0  sel1
  22      -     -    D    --     OUTPUT                0    1    0    0  sel2


Code:

s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable


Device-Specific Information:     d:\我的文档\zyl\37\s8\jiaotongdengkongzhi.rpt
jiaotongdengkongzhi

** BURIED LOGIC **

                                                    Fan-In    Fan-Out
 IOC     LC     EC   Row  Col  Primitive    Code      INP  FBK  OUT  FBK  Name
   -      8     -    E    09       DFFE                1    3    0    5  |CNT05S:1|CNT3B2 (|CNT05S:1|:12)
   -      7     -    E    09       DFFE                1    3    0    5  |CNT05S:1|CNT3B1 (|CNT05S:1|:13)
   -      6     -    E    09       DFFE                1    3    0    3  |CNT05S:1|CNT3B0 (|CNT05S:1|:14)
   -      5     -    E    09       AND2        !       0    2    0    5  |CNT05S:1|:42
   -      2     -    E    09       AND2                0    2    0    4  |CNT05S:1|:451
   -      4     -    E    09       AND2                0    2    0    4  |CNT05S:1|:471
   -      1     -    E    09        OR2                0    3    0    4  |CNT05S:1|:487
   -      8     -    E    24       AND2                0    2    0    8  |CNT25S:2|LPM_ADD_SUB:88|addcore:adder|:59
   -      5     -    E    24       AND2                0    2    0    1  |CNT25S:2|LPM_ADD_SUB:88|addcore:adder|:63
   -      7     -    E    24       AND2                0    3    0    1  |CNT25S:2|LPM_ADD_SUB:88|addcore:adder|:67
   -      6     -    E    24       DFFE                1    3    0   27  |CNT25S:2|CNT5B4 (|CNT25S:2|:19)
   -      4     -    E    24       DFFE                1    3    0   18  |CNT25S:2|CNT5B3 (|CNT25S:2|:20)
   -      3     -    E    24       DFFE                1    3    0   19  |CNT25S:2|CNT5B2 (|CNT25S:2|:21)
   -      1     -    E    24       DFFE                1    3    0   11  |CNT25S:2|CNT5B1 (|CNT25S:2|:22)
   -      2     -    E    24       DFFE                1    2    0   11  |CNT25S:2|CNT5B0 (|CNT25S:2|:23)
   -      1     -    E    20        OR2        !       0    4    0    8  |CNT25S:2|:54
   -      1     -    E    13       AND2                0    4    0    4  |CNT25S:2|:1548
   -      8     -    E    18       AND2    s           0    3    0    6  |CNT25S:2|~1562~1
   -      2     -    E    20       AND2                0    4    0    5  |CNT25S:2|:1590
   -      2     -    E    13       AND2    s           0    3    0   10  |CNT25S:2|~1646~1
   -      4     -    E    19       AND2                0    3    0    3  |CNT25S:2|:1646
   -      4     -    E    13       AND2                0    4    0    5  |CNT25S:2|:1660
   -      6     -    E    18       AND2                0    4    0    5  |CNT25S:2|:1674
   -      7     -    E    18       AND2                0    4    0    5  |CNT25S:2|:1688
   -      3     -    E    20       AND2                0    4    0    5  |CNT25S:2|:1702
   -      1     -    E    23       AND2                0    2    0    6  |CNT25S:2|:1716
   -      3     -    E    18       AND2                0    2    0    5  |CNT25S:2|:1730
   -      3     -    E    19       AND2                0    2    0    5  |CNT25S:2|:1744
   -      2     -    E    18       AND2    s           0    3    0    5  |CNT25S:2|~1758~1
   -      7     -    E    20       AND2                0    2    0    5  |CNT25S:2|:1758
   -      3     -    E    13       AND2                0    4    0    8  |CNT25S:2|:1772
   -      7     -    E    16       AND2                0    2    0    4  |CNT25S:2|:1786
   -      1     -    E    18        OR2    s   !       0    3    0    9  |CNT25S:2|~1800~1
   -      5     -    E    20        OR2        !       0    4    0    4  |CNT25S:2|:1814
   -      5     -    E    13        OR2        !       0    4    0    4  |CNT25S:2|:1828
   -      7     -    E    19        OR2    s   !       0    2    0    4  |CNT25S:2|~1842~1
   -      5     -    E    18        OR2        !       0    4    0    7  |CNT25S:2|:1842
   -      1     -    E    19        OR2    s   !       0    2    0    6  |CNT25S:2|~1856~1
   -      4     -    E    18        OR2        !       0    4    0    5  |CNT25S:2|:1856
   -      4     -    E    20        OR2    s   !       0    2    0    6  |CNT25S:2|~1870~1
   -      6     -    E    20        OR2        !       0    4    0    4  |CNT25S:2|:1870
   -      8     -    E    08       AND2    s   !       0    2    0    3  |CNT25S:2|~2029~1
   -      6     -    E    02        OR2        !       0    4    0    4  |CNT25S:2|:2029
   -      6     -    E    23        OR2    s           0    3    0    2  |CNT25S:2|~2089~1
   -      2     -    E    14        OR2    s           0    2    0    2  |CNT25S:2|~2089~2
   -      7     -    E    14        OR2                0    4    0    1  |CNT25S:2|:2166
   -      8     -    E    16        OR2    s           0    3    0    3  |CNT25S:2|~2209~1
   -      5     -    E    22        OR2    s           0    3    0    1  |CNT25S:2|~2232~1
   -      8     -    E    17       AND2    s   !       0    2    0    1  |CNT25S:2|~2239~1
   -      3     -    E    23        OR2                0    4    0    1  |CNT25S:2|:2239
   -      5     -    E    11       AND2    s           0    2    0    4  |CNT25S:2|~2262~1
   -      4     -    E    23       AND2                0    4    0    1  |CNT25S:2|:2262
   -      8     -    E    13        OR2                0    4    0    1  |CNT25S:2|:2286
   -      7     -    E    13        OR2    s           0    3    0    1  |CNT25S:2|~2304~1
   -      3     -    E    21        OR2                0    4    0    1  |CNT25S:2|:2305
   -      1     -    E    15        OR2                0    3    0    1  |CNT25S:2|:2317
   -      6     -    E    16        OR2    s           0    3    0    3  |CNT25S:2|~2334~1
   -      2     -    E    11       AND2                0    4    0    1  |CNT25S:2|:2334
   -      5     -    E    16        OR2                0    2    0    1  |CNT25S:2|:2359
   -      4     -    E    16        OR2                0    4    0    1  |CNT25S:2|:2361
   -      6     -    E    21        OR2                0    3    0    1  |CNT25S:2|:2371
   -      1     -    E    21        OR2                0    4    0    1  |CNT25S:2|:2385
   -      1     -    E    17        OR2                0    4    0    1  |CNT25S:2|:2389
   -      5     -    E    17        OR2                0    4    0    1  |CNT25S:2|:2403
   -      2     -    E    07        OR2                0    4    0    1  |CNT25S:2|:2409
   -      3     -    E    07        OR2                0    4    0    1  |CNT25S:2|:2413
   -      4     -    E    02        OR2                0    2    0    1  |CNT25S:2|:2653
   -      4     -    E    22        OR2    s           0    2    0    3  |CNT25S:2|~2698~1
   -      7     -    E    07        OR2                0    4    0    1  |CNT25S:2|:2731
   -      2     -    E    22        OR2    s           0    4    0    1  |CNT25S:2|~2733~1
   -      5     -    E    08        OR2    s   !       0    2    0    1  |CNT25S:2|~2733~2
   -      2     -    E    16        OR2                0    3    0    2  |CNT25S:2|:2746
   -      5     -    E    21        OR2    s   !       0    3    0    3  |CNT25S:2|~2775~1
   -      7     -    E    21       AND2    s           0    2    0    1  |CNT25S:2|~2775~2
   -      7     -    E    22        OR2    s   !       0    2    0    2  |CNT25S:2|~2775~3
   -      2     -    E    19        OR2    s           0    4    0    1  |CNT25S:2|~2775~4
   -      1     -    E    22        OR2                0    4    0    1  |CNT25S:2|:2776
   -      1     -    E    02       AND2    s           0    4    0    2  |CNT25S:2|~2805~1
   -      2     -    E    02        OR2    s           0    4    0    2  |CNT25S:2|~2805~2

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