📄 jiaotongdengkongzhi.rpt
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FLEX 10K Configuration Scheme: Passive Serial
Device Options:
User-Supplied Start-Up Clock = OFF
Auto-Restart Configuration on Frame Error = OFF
Release Clears Before Tri-States = OFF
Enable Chip_Wide Reset = OFF
Enable Chip-Wide Output Enable = OFF
Enable INIT_DONE Output = OFF
JTAG User Code = 7f
MultiVolt I/O = OFF
R R R R R R R R R R R R R R R R R R R R R R R R R R R
E E E E E E E E E E E E E E E E E E E E E E E E E E E
S S S S S S S S S S S S S S G G G G V S S S S S S S S S S S S S
E E E E E G E E E E V E E E E G E N N N N C E E E E E E E V E E E E E E
R R R R R N R R R R C R R R R N R D D D D C R R R R R R R C R R R R R R
V V V V V D V V V V C V V V V D V I I I I I V V V V V V V C V V V V V V
E E E E E I E E E E I E E E E I E N N N N N E E E E E E E I E E E E E E
D D D D D O D D D D O D D D D O D T T T T T D D D D D D D O D D D D D D
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/ 144 142 140 138 136 134 132 130 128 126 124 122 120 118 116 114 112 110 |_
/ 143 141 139 137 135 133 131 129 127 125 123 121 119 117 115 113 111 109 |
#TCK | 1 108 | ^DATA0
^CONF_DONE | 2 107 | ^DCLK
^nCEO | 3 106 | ^nCE
#TDO | 4 105 | #TDI
VCCIO | 5 104 | GNDIO
VCCINT | 6 103 | GNDINT
sb | 7 102 | RESERVED
RESERVED | 8 101 | RESERVED
RESERVED | 9 100 | RESERVED
RESERVED | 10 99 | RESERVED
RESERVED | 11 98 | led6
RESERVED | 12 97 | led5
RESERVED | 13 96 | led4
RESERVED | 14 95 | led3
GNDIO | 15 94 | VCCIO
GNDINT | 16 93 | VCCINT
RESERVED | 17 92 | led2
RESERVED | 18 91 | led1
RESERVED | 19 EPF10K20TC144-4 90 | led0
sel0 | 20 89 | RESERVED
sel1 | 21 88 | RESERVED
sel2 | 22 87 | RESERVED
clk | 23 86 | RESERVED
VCCIO | 24 85 | GNDIO
VCCINT | 25 84 | GNDINT
disclk | 26 83 | RESERVED
RESERVED | 27 82 | RESERVED
RESERVED | 28 81 | RESERVED
RESERVED | 29 80 | RESERVED
RESERVED | 30 79 | RESERVED
mg | 31 78 | RESERVED
my | 32 77 | ^MSEL0
mr | 33 76 | ^MSEL1
#TMS | 34 75 | VCCINT
^nSTATUS | 35 74 | ^nCONFIG
bg | 36 73 | RESERVED
| 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 _|
\ 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 |
\---------------------------------------------------------------------------
b b R G R R R R V R R R R G R V V G G G G G R R V R R R R G R R R R V R
y r E N E E E E C E E E E N E C C N N N N N E E C E E E E N E E E E C E
S D S S S S C S S S S D S C C D D D D D S S C S S S S D S S S S C S
E I E E E E I E E E E I E I I I I I I I E E I E E E E I E E E E I E
R O R R R R O R R R R O R N N N N N N N R R O R R R R O R R R R O R
V V V V V V V V V V T T T T T T T V V V V V V V V V V V
E E E E E E E E E E E E E E E E E E E E E
D D D D D D D D D D D D D D D D D D D D D
N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
GNDINT = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
GNDIO = Dedicated ground pin, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
^ = Dedicated configuration pin.
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin.
@ = Special-purpose pin.
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions.
Device-Specific Information: d:\我的文档\zyl\37\s8\jiaotongdengkongzhi.rpt
jiaotongdengkongzhi
** RESOURCE USAGE **
Logic Column Row
Array Interconnect Interconnect Clears/ External
Block Logic Cells Driven Driven Clocks Presets Interconnect
A1 8/ 8(100%) 3/ 8( 37%) 1/ 8( 12%) 0/2 0/2 18/22( 81%)
A2 8/ 8(100%) 1/ 8( 12%) 6/ 8( 75%) 0/2 0/2 10/22( 45%)
A3 8/ 8(100%) 2/ 8( 25%) 0/ 8( 0%) 0/2 0/2 17/22( 77%)
A4 7/ 8( 87%) 1/ 8( 12%) 4/ 8( 50%) 0/2 0/2 14/22( 63%)
A5 8/ 8(100%) 2/ 8( 25%) 2/ 8( 25%) 0/2 0/2 18/22( 81%)
A6 7/ 8( 87%) 1/ 8( 12%) 6/ 8( 75%) 0/2 0/2 6/22( 27%)
A7 8/ 8(100%) 3/ 8( 37%) 2/ 8( 25%) 1/2 0/2 16/22( 72%)
A8 8/ 8(100%) 2/ 8( 25%) 7/ 8( 87%) 0/2 0/2 5/22( 22%)
A9 8/ 8(100%) 3/ 8( 37%) 1/ 8( 12%) 0/2 0/2 11/22( 50%)
A10 8/ 8(100%) 3/ 8( 37%) 7/ 8( 87%) 0/2 0/2 9/22( 40%)
A11 6/ 8( 75%) 1/ 8( 12%) 4/ 8( 50%) 0/2 0/2 8/22( 36%)
A12 8/ 8(100%) 5/ 8( 62%) 2/ 8( 25%) 0/2 0/2 10/22( 45%)
A13 3/ 8( 37%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 10/22( 45%)
A14 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 0/2 0/2 12/22( 54%)
A15 8/ 8(100%) 0/ 8( 0%) 8/ 8(100%) 0/2 0/2 7/22( 31%)
A16 7/ 8( 87%) 0/ 8( 0%) 6/ 8( 75%) 0/2 0/2 6/22( 27%)
A17 6/ 8( 75%) 1/ 8( 12%) 6/ 8( 75%) 0/2 0/2 4/22( 18%)
A18 8/ 8(100%) 0/ 8( 0%) 2/ 8( 25%) 0/2 0/2 19/22( 86%)
A19 8/ 8(100%) 1/ 8( 12%) 4/ 8( 50%) 0/2 0/2 11/22( 50%)
A20 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 4/22( 18%)
A21 7/ 8( 87%) 0/ 8( 0%) 4/ 8( 50%) 0/2 0/2 12/22( 54%)
A22 8/ 8(100%) 0/ 8( 0%) 6/ 8( 75%) 0/2 0/2 10/22( 45%)
A23 8/ 8(100%) 1/ 8( 12%) 6/ 8( 75%) 0/2 0/2 6/22( 27%)
A24 8/ 8(100%) 1/ 8( 12%) 5/ 8( 62%) 1/2 0/2 6/22( 27%)
B1 8/ 8(100%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 4/22( 18%)
B6 4/ 8( 50%) 1/ 8( 12%) 3/ 8( 37%) 0/2 0/2 4/22( 18%)
B12 8/ 8(100%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 5/22( 22%)
C9 2/ 8( 25%) 0/ 8( 0%) 2/ 8( 25%) 0/2 0/2 4/22( 18%)
C14 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 1/2 0/2 6/22( 27%)
C17 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 1/2 0/2 9/22( 40%)
C18 2/ 8( 25%) 0/ 8( 0%) 2/ 8( 25%) 0/2 0/2 3/22( 13%)
C21 2/ 8( 25%) 2/ 8( 25%) 0/ 8( 0%) 1/2 0/2 2/22( 9%)
C22 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 1/2 0/2 10/22( 45%)
C23 8/ 8(100%) 6/ 8( 75%) 5/ 8( 62%) 1/2 0/2 4/22( 18%)
D3 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 2/22( 9%)
D20 8/ 8(100%) 4/ 8( 50%) 3/ 8( 37%) 1/2 0/2 4/22( 18%)
D22 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 1/2 0/2 1/22( 4%)
E1 8/ 8(100%) 1/ 8( 12%) 0/ 8( 0%) 1/2 0/2 15/22( 68%)
E2 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 0/2 0/2 17/22( 77%)
E3 2/ 8( 25%) 0/ 8( 0%) 2/ 8( 25%) 0/2 0/2 4/22( 18%)
E4 8/ 8(100%) 1/ 8( 12%) 0/ 8( 0%) 1/2 0/2 18/22( 81%)
E5 8/ 8(100%) 1/ 8( 12%) 1/ 8( 12%) 1/2 0/2 14/22( 63%)
E6 8/ 8(100%) 1/ 8( 12%) 0/ 8( 0%) 1/2 0/2 19/22( 86%)
E7 8/ 8(100%) 1/ 8( 12%) 1/ 8( 12%) 0/2 0/2 20/22( 90%)
E8 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 0/2 0/2 11/22( 50%)
E9 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 1/2 0/2 5/22( 22%)
E10 8/ 8(100%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 18/22( 81%)
E11 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 0/2 0/2 14/22( 63%)
E12 8/ 8(100%) 1/ 8( 12%) 4/ 8( 50%) 0/2 0/2 14/22( 63%)
E13 8/ 8(100%) 0/ 8( 0%) 7/ 8( 87%) 0/2 0/2 8/22( 36%)
E14 8/ 8(100%) 0/ 8( 0%) 2/ 8( 25%) 0/2 0/2 13/22( 59%)
E15 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 3/22( 13%)
E16 8/ 8(100%) 0/ 8( 0%) 7/ 8( 87%) 0/2 0/2 7/22( 31%)
E17 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 0/2 0/2 11/22( 50%)
E18 8/ 8(100%) 0/ 8( 0%) 8/ 8(100%) 0/2 0/2 5/22( 22%)
E19 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 0/2 0/2 9/22( 40%)
E20 7/ 8( 87%) 0/ 8( 0%) 6/ 8( 75%) 0/2 0/2 6/22( 27%)
E21 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 0/2 0/2 10/22( 45%)
E22 8/ 8(100%) 0/ 8( 0%) 6/ 8( 75%) 0/2 0/2 12/22( 54%)
E23 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 0/2 0/2 16/22( 72%)
E24 8/ 8(100%) 0/ 8( 0%) 6/ 8( 75%) 1/2 0/2 3/22( 13%)
F6 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 2/22( 9%)
F14 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 2/22( 9%)
Embedded Column Row
Array Embedded Interconnect Interconnect Read/ External
Block Cells Driven Driven Clocks Write Interconnect
Total dedicated input pins used: 0/6 ( 0%)
Total I/O pins used: 19/96 ( 19%)
Total logic cells used: 427/1152 ( 37%)
Total embedded cells used: 0/48 ( 0%)
Total EABs used: 0/6 ( 0%)
Average fan-in: 3.39/4 ( 84%)
Total fan-in: 1450/4608 ( 31%)
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