📄 cnt45s.rpt
字号:
- 2 - A 20 AND2 s 0 2 0 20 ~76~2
- 5 - A 22 AND2 s 2 0 0 2 ~76~3
- 8 - A 19 AND2 0 3 0 8 :76
- 5 - A 10 AND2 s 0 4 0 8 ~2769~1
- 1 - A 16 OR2 ! 0 2 0 1 :2785
- 4 - A 20 AND2 s 0 2 0 12 ~2817~1
- 7 - A 21 AND2 0 3 0 4 :2833
- 2 - A 21 OR2 ! 0 3 0 6 :2849
- 5 - A 12 AND2 0 3 0 6 :2865
- 1 - A 21 OR2 ! 0 3 0 6 :2881
- 3 - A 10 AND2 s 0 4 0 9 ~2929~1
- 1 - A 24 AND2 0 2 0 4 :2929
- 1 - B 23 OR2 ! 0 2 0 6 :2945
- 3 - A 13 AND2 0 3 0 6 :2961
- 5 - A 14 OR2 ! 0 2 0 5 :2977
- 5 - A 05 OR2 s ! 0 3 0 6 ~2993~1
- 5 - A 19 OR2 ! 0 2 0 4 :3009
- 2 - A 05 AND2 s 0 3 0 10 ~3041~1
- 7 - A 05 AND2 s 0 3 0 4 ~3089~1
- 3 - A 05 AND2 0 2 0 5 :3089
- 8 - A 10 OR2 s ! 0 2 0 14 ~3105~1
- 2 - A 08 OR2 ! 0 2 0 4 :3105
- 2 - A 12 AND2 0 2 0 5 :3121
- 3 - A 12 OR2 s ! 0 3 0 7 ~3137~1
- 1 - A 03 OR2 ! 0 2 0 4 :3137
- 1 - A 05 AND2 0 4 0 5 :3153
- 8 - A 05 OR2 ! 0 4 0 5 :3169
- 6 - A 05 AND2 0 4 0 6 :3185
- 1 - A 12 OR2 ! 0 4 0 6 :3201
- 2 - A 13 AND2 0 3 0 5 :3217
- 2 - A 03 OR2 ! 0 2 0 5 :3233
- 2 - A 10 OR2 s ! 0 4 0 3 ~3249~1
- 3 - A 03 AND2 0 2 0 4 :3249
- 1 - A 19 AND2 s 0 3 0 4 ~3265~1
- 2 - A 19 OR2 ! 0 3 0 6 :3265
- 1 - A 10 AND2 s 0 4 0 9 ~3281~1
- 5 - A 21 AND2 0 3 0 6 :3345
- 4 - A 05 OR2 s ! 0 3 0 4 ~3361~1
- 8 - A 21 OR2 ! 0 3 0 7 :3361
- 6 - A 12 AND2 s 0 3 0 3 ~3377~1
- 4 - A 12 AND2 0 3 0 5 :3377
- 6 - A 07 AND2 0 2 0 4 :3409
- 3 - A 06 OR2 ! 0 2 0 3 :3425
- 7 - A 10 AND2 s 0 4 0 7 ~3441~1
- 3 - A 07 OR2 ! 0 2 0 4 :3457
- 1 - A 07 OR2 s 0 4 0 3 ~3598~1
- 6 - C 10 OR2 s 0 3 0 3 ~3598~2
- 4 - A 07 OR2 0 4 1 4 :3598
- 1 - A 08 AND2 s ! 0 2 0 5 ~3718~1
- 3 - A 23 OR2 s 0 4 0 2 ~3718~2
- 6 - A 23 AND2 s ! 0 2 0 2 ~3718~3
- 2 - A 16 AND2 s ! 0 4 0 2 ~3718~4
- 1 - A 23 OR2 0 4 1 0 :3738
- 4 - A 18 OR2 s 0 4 0 4 ~3796~1
- 1 - A 15 AND2 s ! 0 4 0 2 ~3796~2
- 3 - A 14 OR2 s ! 0 4 0 5 ~3831~1
- 1 - A 01 OR2 s ! 0 3 0 3 ~3856~1
- 8 - A 01 OR2 s ! 0 4 0 2 ~3856~2
- 7 - A 23 OR2 s 0 4 0 1 ~3856~3
- 2 - A 23 OR2 0 4 1 0 :3876
- 6 - A 21 AND2 ! 0 2 0 3 :3904
- 4 - A 23 OR2 0 4 0 1 :3934
- 5 - A 23 OR2 0 4 0 1 :3964
- 8 - A 23 OR2 0 4 1 0 :4014
- 5 - A 18 OR2 s ! 0 3 0 3 ~4036~1
- 3 - A 18 OR2 ! 0 4 0 2 :4036
- 5 - A 15 AND2 0 4 0 1 :4059
- 3 - A 24 OR2 s ! 0 3 0 1 ~4066~1
- 6 - A 15 OR2 s 0 4 0 1 ~4089~1
- 7 - A 15 OR2 0 4 0 1 :4089
- 3 - A 04 AND2 s ! 0 2 0 1 ~4096~1
- 2 - A 11 OR2 s ! 0 3 0 5 ~4119~1
- 8 - A 15 AND2 s 0 3 0 1 ~4119~2
- 3 - A 15 OR2 0 4 0 1 :4119
- 6 - A 01 OR2 s ! 0 3 0 5 ~4126~1
- 4 - A 01 OR2 s 0 4 0 1 ~4126~2
- 6 - A 06 AND2 s 0 4 0 1 ~4149~1
- 8 - A 06 OR2 0 4 1 0 :4150
- 6 - A 18 AND2 0 3 0 1 :4173
- 7 - A 18 OR2 0 3 0 1 :4174
- 2 - A 18 OR2 s 0 4 0 1 ~4191~1
- 8 - A 18 OR2 0 4 0 1 :4192
- 6 - A 19 OR2 s 0 4 0 1 ~4204~1
- 7 - A 19 OR2 0 4 0 1 :4204
- 3 - A 19 OR2 s 0 4 0 1 ~4221~1
- 4 - A 19 OR2 0 4 0 1 :4222
- 5 - A 03 OR2 0 4 0 1 :4233
- 6 - A 03 OR2 0 3 0 1 :4234
- 7 - A 03 AND2 0 4 0 1 :4251
- 8 - A 03 OR2 0 4 0 1 :4252
- 4 - A 03 OR2 0 3 0 1 :4264
- 2 - A 07 AND2 s 0 2 0 2 ~4281~1
- 5 - A 06 AND2 0 3 0 1 :4281
- 1 - A 06 OR2 0 4 1 0 :4290
- 5 - A 13 OR2 0 4 0 1 :4306
- 7 - A 13 OR2 0 4 0 1 :4320
- 6 - A 13 OR2 0 4 0 1 :4326
- 2 - A 24 OR2 0 4 0 1 :4332
- 1 - A 14 OR2 0 4 0 1 :4336
- 2 - A 14 OR2 0 4 0 1 :4342
- 6 - A 14 OR2 0 3 0 1 :4354
- 8 - A 14 OR2 0 4 0 1 :4368
- 3 - A 02 OR2 0 4 0 1 :4372
- 4 - A 02 OR2 0 4 0 1 :4386
- 5 - A 02 OR2 0 4 0 1 :4390
- 6 - A 02 OR2 0 3 0 1 :4402
- 8 - A 02 OR2 0 4 0 1 :4414
- 7 - A 02 OR2 0 4 0 1 :4416
- 1 - A 02 OR2 0 3 1 0 :4426
- 3 - A 01 OR2 0 4 1 1 :4702
- 4 - C 22 OR2 s ! 0 3 0 5 ~4807~1
- 2 - A 15 AND2 s ! 0 3 0 3 ~4807~2
- 6 - A 09 OR2 s 0 4 0 2 ~4807~3
- 7 - A 09 AND2 s ! 0 2 0 1 ~4807~4
- 2 - A 09 OR2 0 4 1 0 :4842
- 4 - A 14 OR2 s 0 4 0 4 ~4920~1
- 2 - A 02 AND2 s ! 0 3 0 3 ~4945~1
- 8 - A 04 AND2 s ! 0 2 0 4 ~4945~2
- 4 - A 15 AND2 s ! 0 3 0 2 ~4945~3
- 8 - A 09 OR2 0 4 0 1 :4945
- 5 - A 09 OR2 0 4 1 0 :4978
- 8 - A 07 AND2 s 0 2 0 1 ~4980~1
- 7 - A 01 AND2 s 0 4 0 2 ~4980~2
- 6 - A 17 OR2 ! 0 3 0 2 :4993
- 1 - A 18 AND2 s 0 4 0 2 ~5022~1
- 1 - A 09 OR2 0 4 0 1 :5052
- 4 - A 09 OR2 0 4 0 1 :5083
- 5 - A 01 OR2 s ! 0 3 0 3 ~5112~1
- 3 - A 09 OR2 0 4 1 0 :5118
- 1 - A 17 OR2 0 3 0 2 :5125
- 3 - A 16 AND2 0 4 0 1 :5148
- 4 - A 16 OR2 s 0 4 0 1 ~5178~1
- 6 - A 16 OR2 0 4 0 1 :5178
- 7 - A 16 OR2 s 0 3 0 1 ~5185~1
- 7 - A 08 AND2 s 0 2 0 3 ~5208~1
- 8 - A 16 OR2 0 4 0 1 :5208
- 1 - C 15 AND2 s 0 2 0 2 ~5238~1
- 5 - A 16 OR2 0 4 0 1 :5238
- 5 - A 07 OR2 s 0 4 0 3 ~5245~1
- 2 - A 06 AND2 s 0 2 0 2 ~5256~1
- 7 - A 06 OR2 0 4 1 0 :5256
- 2 - A 17 AND2 0 3 0 1 :5280
- 5 - A 24 OR2 s 0 3 0 1 ~5292~1
- 6 - A 24 OR2 0 4 0 1 :5292
- 7 - A 24 OR2 0 4 0 1 :5293
- 4 - B 17 AND2 s 0 2 0 4 ~5310~1
- 8 - A 24 OR2 s 0 3 0 1 ~5311~1
- 4 - A 24 OR2 0 4 0 1 :5311
- 2 - A 04 OR2 0 4 0 1 :5322
- 4 - A 04 OR2 s 0 3 0 1 ~5323~1
- 7 - A 04 OR2 0 4 0 1 :5340
- 5 - A 04 OR2 0 3 0 1 :5341
- 8 - A 11 AND2 0 3 0 1 :5352
- 3 - A 11 OR2 0 3 0 1 :5353
- 2 - A 01 OR2 0 4 0 1 :5371
- 4 - A 06 OR2 s 0 3 0 3 ~5394~1
- 7 - A 07 OR2 0 4 1 0 :5394
- 4 - A 21 OR2 0 3 0 1 :5413
- 3 - A 21 OR2 0 4 0 1 :5427
- 6 - A 20 OR2 0 4 0 1 :5431
- 7 - A 20 OR2 0 4 0 1 :5445
- 8 - A 20 OR2 0 4 0 1 :5451
- 5 - A 20 OR2 0 3 0 1 :5463
- 7 - A 14 OR2 0 4 0 1 :5467
- 1 - A 04 OR2 0 4 0 1 :5481
- 6 - A 04 OR2 0 4 0 1 :5485
- 4 - A 11 OR2 0 4 0 1 :5499
- 5 - A 11 OR2 0 3 0 1 :5511
- 6 - A 11 OR2 0 4 0 1 :5515
- 7 - A 11 OR2 0 4 0 1 :5523
- 1 - A 11 OR2 0 3 1 0 :5532
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: d:\我的文档\zyl\37\s8\cnt45s.rpt
cnt45s
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 61/ 96( 63%) 25/ 48( 52%) 29/ 48( 60%) 0/16( 0%) 9/16( 56%) 0/16( 0%)
B: 1/ 96( 1%) 0/ 48( 0%) 3/ 48( 6%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
C: 4/ 96( 4%) 1/ 48( 2%) 2/ 48( 4%) 0/16( 0%) 1/16( 6%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
06: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
10: 3/24( 12%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 3/24( 12%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
24: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: d:\我的文档\zyl\37\s8\cnt45s.rpt
cnt45s
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 6 CLK
Device-Specific Information: d:\我的文档\zyl\37\s8\cnt45s.rpt
cnt45s
** EQUATIONS **
CLK : INPUT;
EN45 : INPUT;
SB : INPUT;
-- Node name is ':25' = 'CNT6B0'
-- Equation name is 'CNT6B0', location is LC2_A22, type is buried.
CNT6B0 = DFFE( _EQ001, GLOBAL( CLK), VCC, VCC, VCC);
_EQ001 = !CNT6B0 & !_LC8_A19
# !EN45 & !_LC8_A19 & SB;
-- Node name is ':24' = 'CNT6B1'
-- Equation name is 'CNT6B1', location is LC1_A22, type is buried.
CNT6B1 = DFFE( _EQ002, GLOBAL( CLK), VCC, VCC, VCC);
_EQ002 = _LC3_A20 & !_LC8_A19
# _LC2_A20 & !_LC8_A19
# _LC5_A22 & !_LC8_A19;
-- Node name is ':23' = 'CNT6B2'
-- Equation name is 'CNT6B2', location is LC3_A22, type is buried.
CNT6B2 = DFFE( _EQ003, GLOBAL( CLK), VCC, VCC, VCC);
_EQ003 = !EN45 & !_LC8_A19 & SB
# _LC6_A22 & !_LC8_A19
# _LC8_A19 & !SB
# _LC6_A22 & !SB;
-- Node name is ':22' = 'CNT6B3'
-- Equation name is 'CNT6B3', location is LC4_A22, type is buried.
CNT6B3 = DFFE( _EQ004, GLOBAL( CLK), VCC, VCC, VCC);
_EQ004 = !_LC8_A19 & _LC8_A22
# !EN45 & !_LC8_A19 & SB
# _LC8_A22 & !SB
# _LC8_A19 & !SB;
-- Node name is ':21' = 'CNT6B4'
-- Equation name is 'CNT6B4', location is LC1_A13, type is buried.
CNT6B4 = DFFE( _EQ005, GLOBAL( CLK), VCC, VCC, VCC);
_EQ005 = !CNT6B4 & _LC4_A13 & !_LC8_A19
# CNT6B4 & !_LC4_A13 & !_LC8_A19
# _LC5_A22 & !_LC8_A19;
-- Node name is ':20' = 'CNT6B5'
-- Equation name is 'CNT6B5', location is LC7_A22, type is buried.
CNT6B5 = DFFE( _EQ006, GLOBAL( CLK), VCC, VCC, VCC);
_EQ006 = _LC8_A13 & !_LC8_A19
# !EN45 & !_LC8_A19 & SB
# _LC8_A13 & !SB
# _LC8_A19 & !SB;
-- Node name is 'DOUT45B0'
-- Equation name is 'DOUT45B0', type is output
DOUT45B0 = _LC1_A11;
-- Node name is 'DOUT45B1'
-- Equation name is 'DOUT45B1', type is output
DOUT45B1 = _LC7_A7;
-- Node name is 'DOUT45B2'
-- Equation name is 'DOUT45B2', type is output
DOUT45B2 = _LC7_A6;
-- Node name is 'DOUT45B3'
-- Equation name is 'DOUT45B3', type is output
DOUT45B3 = _LC3_A9;
-- Node name is 'DOUT45B4'
-- Equation name is 'DOUT45B4', type is output
DOUT45B4 = _LC5_A9;
-- Node name is 'DOUT45B5'
-- Equation name is 'DOUT45B5', type is output
DOUT45B5 = _LC2_A9;
-- Node name is 'DOUT45B6'
-- Equation name is 'DOUT45B6', type is output
DOUT45B6 = _LC3_A1;
-- Node name is 'DOUT45B7'
-- Equation name is 'DOUT45B7', type is output
DOUT45B7 = GND;
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