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📄 xskz.rpt

📁 课程设计《交通灯控制的设计》
💻 RPT
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字号:
   -      1     -    A    04       AND2                2    0    0    2  :591
   -      8     -    C    02        OR2                3    1    0    1  :592
   -      1     -    C    02        OR2                2    2    1    1  :593
   -      7     -    B    17        OR2                2    1    0    1  :599
   -      4     -    B    17       AND2                2    0    0    2  :606
   -      8     -    B    17        OR2                3    1    0    1  :607
   -      2     -    B    17        OR2                2    2    1    1  :608
   -      7     -    B    18        OR2                2    1    0    1  :614
   -      3     -    B    18       AND2                2    0    0    2  :621
   -      8     -    B    18        OR2                3    1    0    1  :622
   -      4     -    B    18        OR2                2    2    1    1  :623
   -      6     -    B    24        OR2                2    1    0    1  :629
   -      3     -    B    24       AND2                2    0    0    2  :636
   -      7     -    B    24        OR2                3    1    0    1  :637
   -      8     -    B    24        OR2                2    2    1    1  :638
   -      6     -    A    04        OR2                2    1    0    1  :644
   -      3     -    A    04       AND2                2    0    0    2  :651
   -      8     -    A    04        OR2                3    1    0    1  :652
   -      2     -    A    04        OR2                2    2    1    1  :653
   -      3     -    C    12        OR2                2    1    0    1  :659
   -      5     -    C    12        OR2                3    1    0    1  :667
   -      1     -    C    12        OR2                2    2    1    1  :668
   -      1     -    B    24        OR2                2    1    0    1  :674
   -      5     -    B    18        OR2                3    1    0    1  :682
   -      1     -    B    18        OR2                2    2    1    1  :683
   -      6     -    C    12        OR2                2    1    0    1  :689
   -      5     -    C    02        OR2                3    1    0    1  :697
   -      6     -    C    02        OR2                2    2    1    1  :698
   -      3     -    C    02        OR2                2    1    0    1  :704
   -      4     -    C    02        OR2                3    1    0    1  :712
   -      2     -    C    02        OR2                2    2    1    1  :713
   -      5     -    B    17        OR2                2    1    0    1  :719
   -      6     -    B    17        OR2                3    1    0    1  :727
   -      3     -    B    17        OR2                2    2    1    1  :728
   -      2     -    B    18        OR2                2    1    0    1  :734
   -      1     -    B    17        OR2                3    1    0    1  :742
   -      6     -    B    18        OR2                2    2    1    1  :743
   -      4     -    B    24        OR2                2    1    0    1  :749
   -      5     -    B    24        OR2                3    1    0    1  :757
   -      2     -    B    24        OR2                2    2    1    1  :758
   -      4     -    A    04        OR2                2    1    0    1  :764
   -      5     -    A    04        OR2                3    1    0    1  :772
   -      7     -    A    04        OR2                2    2    1    1  :773


Code:

s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register


Device-Specific Information:                    d:\我的文档\zyl\37\s8\xskz.rpt
xskz

** FASTTRACK INTERCONNECT UTILIZATION **

Row FastTrack Interconnect:

          Global         Left Half-      Right Half-
         FastTrack       FastTrack       FastTrack 
Row     Interconnect    Interconnect    Interconnect    Input Pins     Output Pins     Bidir Pins
A:       5/ 96(  5%)     2/ 48(  4%)     0/ 48(  0%)    5/16( 31%)      2/16( 12%)     0/16(  0%)
B:      12/ 96( 12%)     0/ 48(  0%)    14/ 48( 29%)    9/16( 56%)      5/16( 31%)     0/16(  0%)
C:      11/ 96( 11%)    10/ 48( 20%)     3/ 48(  6%)   10/16( 62%)      4/16( 25%)     0/16(  0%)


Column FastTrack Interconnect:

         FastTrack                                 
Column  Interconnect    Input Pins     Output Pins     Bidir Pins
01:      1/24(  4%)     1/4( 25%)      0/4(  0%)       0/4(  0%)
02:      1/24(  4%)     0/4(  0%)      1/4( 25%)       0/4(  0%)
03:      1/24(  4%)     1/4( 25%)      0/4(  0%)       0/4(  0%)
04:      1/24(  4%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
05:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
06:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
07:      1/24(  4%)     1/4( 25%)      0/4(  0%)       0/4(  0%)
08:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
09:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
10:      1/24(  4%)     1/4( 25%)      0/4(  0%)       0/4(  0%)
11:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
12:      1/24(  4%)     0/4(  0%)      1/4( 25%)       0/4(  0%)
13:      1/24(  4%)     1/4( 25%)      0/4(  0%)       0/4(  0%)
14:      1/24(  4%)     1/4( 25%)      0/4(  0%)       0/4(  0%)
15:      3/24( 12%)     1/4( 25%)      1/4( 25%)       0/4(  0%)
16:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
17:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
18:      1/24(  4%)     0/4(  0%)      1/4( 25%)       0/4(  0%)
19:      1/24(  4%)     1/4( 25%)      0/4(  0%)       0/4(  0%)
20:      1/24(  4%)     1/4( 25%)      0/4(  0%)       0/4(  0%)
21:      2/24(  8%)     2/4( 50%)      0/4(  0%)       0/4(  0%)
22:      1/24(  4%)     1/4( 25%)      0/4(  0%)       0/4(  0%)
23:      1/24(  4%)     1/4( 25%)      0/4(  0%)       0/4(  0%)
24:      2/24(  8%)     1/4( 25%)      1/4( 25%)       0/4(  0%)
EA:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)


Device-Specific Information:                    d:\我的文档\zyl\37\s8\xskz.rpt
xskz

** EQUATIONS **

AIN25B0  : INPUT;
AIN25B1  : INPUT;
AIN25B2  : INPUT;
AIN25B3  : INPUT;
AIN25B4  : INPUT;
AIN25B5  : INPUT;
AIN25B6  : INPUT;
AIN25B7  : INPUT;
AIN25M0  : INPUT;
AIN25M1  : INPUT;
AIN25M2  : INPUT;
AIN25M3  : INPUT;
AIN25M4  : INPUT;
AIN25M5  : INPUT;
AIN25M6  : INPUT;
AIN25M7  : INPUT;
AIN45B0  : INPUT;
AIN45B1  : INPUT;
AIN45B2  : INPUT;
AIN45B3  : INPUT;
AIN45B4  : INPUT;
AIN45B5  : INPUT;
AIN45B6  : INPUT;
AIN45B7  : INPUT;
AIN45M0  : INPUT;
AIN45M1  : INPUT;
AIN45M2  : INPUT;
AIN45M3  : INPUT;
AIN45M4  : INPUT;
AIN45M5  : INPUT;
AIN45M6  : INPUT;
AIN45M7  : INPUT;
AIN050   : INPUT;
AIN051   : INPUT;
AIN052   : INPUT;
AIN053   : INPUT;
AIN054   : INPUT;
AIN055   : INPUT;
AIN056   : INPUT;
AIN057   : INPUT;
EN05B    : INPUT;
EN05M    : INPUT;
EN25     : INPUT;
EN45     : INPUT;

-- Node name is 'DOUTB0' 
-- Equation name is 'DOUTB0', type is output 
DOUTB0   =  _LC7_A4;

-- Node name is 'DOUTB1' 
-- Equation name is 'DOUTB1', type is output 
DOUTB1   =  _LC2_B24;

-- Node name is 'DOUTB2' 
-- Equation name is 'DOUTB2', type is output 
DOUTB2   =  _LC6_B18;

-- Node name is 'DOUTB3' 
-- Equation name is 'DOUTB3', type is output 
DOUTB3   =  _LC3_B17;

-- Node name is 'DOUTB4' 
-- Equation name is 'DOUTB4', type is output 
DOUTB4   =  _LC2_C2;

-- Node name is 'DOUTB5' 
-- Equation name is 'DOUTB5', type is output 
DOUTB5   =  _LC6_C2;

-- Node name is 'DOUTB6' 
-- Equation name is 'DOUTB6', type is output 
DOUTB6   =  _LC1_B18;

-- Node name is 'DOUTB7' 
-- Equation name is 'DOUTB7', type is output 
DOUTB7   =  _LC1_C12;

-- Node name is 'DOUTM0' 
-- Equation name is 'DOUTM0', type is output 
DOUTM0   =  _LC2_A4;

-- Node name is 'DOUTM1' 
-- Equation name is 'DOUTM1', type is output 
DOUTM1   =  _LC8_B24;

-- Node name is 'DOUTM2' 
-- Equation name is 'DOUTM2', type is output 
DOUTM2   =  _LC4_B18;

-- Node name is 'DOUTM3' 
-- Equation name is 'DOUTM3', type is output 
DOUTM3   =  _LC2_B17;

-- Node name is 'DOUTM4' 
-- Equation name is 'DOUTM4', type is output 
DOUTM4   =  _LC1_C2;

-- Node name is 'DOUTM5' 
-- Equation name is 'DOUTM5', type is output 
DOUTM5   =  _LC4_C12;

-- Node name is 'DOUTM6' 
-- Equation name is 'DOUTM6', type is output 
DOUTM6   =  _LC2_C15;

-- Node name is 'DOUTM7' 
-- Equation name is 'DOUTM7', type is output 
DOUTM7   =  _LC1_C15;

-- Node name is ':530' 
-- Equation name is '_LC6_C15', type is buried 
_LC6_C15 = LCELL( _EQ001);
  _EQ001 = !EN05B &  _LC1_C15
         #  AIN057 &  EN05B;

-- Node name is ':543' 
-- Equation name is '_LC8_C15', type is buried 
_LC8_C15 = LCELL( _EQ002);
  _EQ002 =  AIN057 &  EN05M;

-- Node name is ':544' 
-- Equation name is '_LC7_C15', type is buried 
_LC7_C15 = LCELL( _EQ003);
  _EQ003 = !EN05M & !EN25 &  _LC6_C15
         #  AIN25M7 & !EN05M &  EN25;

-- Node name is ':548' 
-- Equation name is '_LC1_C15', type is buried 
_LC1_C15 = LCELL( _EQ004);
  _EQ004 = !EN45 &  _LC7_C15
         # !EN45 &  _LC8_C15
         #  AIN45M7 &  EN45;

-- Node name is ':554' 
-- Equation name is '_LC4_C15', type is buried 
_LC4_C15 = LCELL( _EQ005);
  _EQ005 = !EN05B &  _LC2_C15
         #  AIN056 &  EN05B;

-- Node name is ':561' 
-- Equation name is '_LC3_C15', type is buried 
_LC3_C15 = LCELL( _EQ006);
  _EQ006 =  AIN056 &  EN05M;

-- Node name is ':562' 
-- Equation name is '_LC5_C15', type is buried 
_LC5_C15 = LCELL( _EQ007);
  _EQ007 = !EN05M & !EN25 &  _LC4_C15
         #  AIN25M6 & !EN05M &  EN25;

-- Node name is ':563' 
-- Equation name is '_LC2_C15', type is buried 
_LC2_C15 = LCELL( _EQ008);
  _EQ008 = !EN45 &  _LC5_C15
         # !EN45 &  _LC3_C15
         #  AIN45M6 &  EN45;

-- Node name is ':569' 
-- Equation name is '_LC7_C12', type is buried 
_LC7_C12 = LCELL( _EQ009);
  _EQ009 = !EN05B &  _LC4_C12
         #  AIN055 &  EN05B;

-- Node name is ':576' 
-- Equation name is '_LC2_C12', type is buried 
_LC2_C12 = LCELL( _EQ010);
  _EQ010 =  AIN055 &  EN05M;

-- Node name is ':577' 
-- Equation name is '_LC8_C12', type is buried 
_LC8_C12 = LCELL( _EQ011);
  _EQ011 = !EN05M & !EN25 &  _LC7_C12
         #  AIN25M5 & !EN05M &  EN25;

-- Node name is ':578' 
-- Equation name is '_LC4_C12', type is buried 
_LC4_C12 = LCELL( _EQ012);
  _EQ012 = !EN45 &  _LC8_C12
         # !EN45 &  _LC2_C12
         #  AIN45M5 &  EN45;

-- Node name is ':584' 
-- Equation name is '_LC7_C2', type is buried 
_LC7_C2  = LCELL( _EQ013);
  _EQ013 = !EN05B &  _LC1_C2
         #  AIN054 &  EN05B;

-- Node name is ':591' 
-- Equation name is '_LC1_A4', type is buried 
_LC1_A4  = LCELL( _EQ014);
  _EQ014 =  AIN054 &  EN05M;

-- Node name is ':592' 
-- Equation name is '_LC8_C2', type is buried 
_LC8_C2  = LCELL( _EQ015);
  _EQ015 = !EN05M & !EN25 &  _LC7_C2
         #  AIN25M4 & !EN05M &  EN25;

-- Node name is ':593' 
-- Equation name is '_LC1_C2', type is buried 
_LC1_C2  = LCELL( _EQ016);
  _EQ016 = !EN45 &  _LC8_C2
         # !EN45 &  _LC1_A4
         #  AIN45M4 &  EN45;

-- Node name is ':599' 
-- Equation name is '_LC7_B17', type is buried 
_LC7_B17 = LCELL( _EQ017);
  _EQ017 = !EN05B &  _LC2_B17
         #  AIN053 &  EN05B;

-- Node name is ':606' 
-- Equation name is '_LC4_B17', type is buried 
_LC4_B17 = LCELL( _EQ018);
  _EQ018 =  AIN053 &  EN05M;

-- Node name is ':607' 
-- Equation name is '_LC8_B17', type is buried 
_LC8_B17 = LCELL( _EQ019);
  _EQ019 = !EN05M & !EN25 &  _LC7_B17
         #  AIN25M3 & !EN05M &  EN25;

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