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Project Information d:\我的文档\zyl\37\s8\xskz.rpt
MAX+plus II Compiler Report File
Version 10.2 07/10/2002
Compiled: 12/27/2007 13:28:15
Copyright (C) 1988-2002 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera. Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner. Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors. No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.
***** Project compilation was successful
XSKZ
** DEVICE SUMMARY **
Chip/ Input Output Bidir Memory Memory LCs
POF Device Pins Pins Pins Bits % Utilized LCs % Utilized
xskz EPF10K10TC144-3 44 16 0 0 0 % 56 9 %
User Pins: 44 16 0
Device-Specific Information: d:\我的文档\zyl\37\s8\xskz.rpt
xskz
***** Logic for device 'xskz' compiled without errors.
Device: EPF10K10TC144-3
FLEX 10K Configuration Scheme: Passive Serial
Device Options:
User-Supplied Start-Up Clock = OFF
Auto-Restart Configuration on Frame Error = OFF
Release Clears Before Tri-States = OFF
Enable Chip_Wide Reset = OFF
Enable Chip-Wide Output Enable = OFF
Enable INIT_DONE Output = OFF
JTAG User Code = 7f
MultiVolt I/O = OFF
R R R R R R R R R R R R R R R
A A A A E E A E E A A E E E E E E E E E E A E
I D I I I S S I D S S I A I G A V S S S S S S S S S A S I S
N O N N N G E E N O V E E N I G N N I E C E E E E E E E V E E I E N E
2 U 4 4 4 N R R 4 U C R R 2 N N 4 D E N N C R R R R R R R C R R N R 4 R
5 T 5 5 5 D V V 5 T C V V 5 0 D 5 I N 0 0 I V V V V V V V C V V 0 V 5 V
M B M B M I E E B B I E E B 5 I M N 2 5 5 N E E E E E E E I E E 5 E B E
6 1 7 3 3 O D D 6 2 O D D 2 1 O 1 T 5 6 B T D D D D D D D O D D 5 D 5 D
--------------------------------------------------------------------------_
/ 144 142 140 138 136 134 132 130 128 126 124 122 120 118 116 114 112 110 |_
/ 143 141 139 137 135 133 131 129 127 125 123 121 119 117 115 113 111 109 |
#TCK | 1 108 | ^DATA0
^CONF_DONE | 2 107 | ^DCLK
^nCEO | 3 106 | ^nCE
#TDO | 4 105 | #TDI
VCCIO | 5 104 | GNDIO
VCCINT | 6 103 | GNDINT
AIN45B0 | 7 102 | RESERVED
AIN25M0 | 8 101 | RESERVED
AIN45M0 | 9 100 | DOUTM0
RESERVED | 10 99 | RESERVED
RESERVED | 11 98 | AIN050
RESERVED | 12 97 | RESERVED
RESERVED | 13 96 | DOUTB0
RESERVED | 14 95 | AIN25B0
GNDIO | 15 94 | VCCIO
GNDINT | 16 93 | VCCINT
DOUTB6 | 17 92 | AIN45B2
DOUTM3 | 18 91 | AIN25B3
DOUTB3 | 19 EPF10K10TC144-3 90 | AIN25M3
DOUTM2 | 20 89 | AIN45B1
DOUTM1 | 21 88 | AIN052
AIN053 | 22 87 | AIN45M2
AIN25M1 | 23 86 | AIN25B1
VCCIO | 24 85 | GNDIO
VCCINT | 25 84 | GNDINT
DOUTM7 | 26 83 | DOUTM4
AIN25B4 | 27 82 | AIN25B5
AIN25B7 | 28 81 | AIN45M5
AIN45B7 | 29 80 | DOUTM5
AIN45M6 | 30 79 | AIN45M4
AIN057 | 31 78 | DOUTB5
AIN25M4 | 32 77 | ^MSEL0
AIN25M7 | 33 76 | ^MSEL1
#TMS | 34 75 | VCCINT
^nSTATUS | 35 74 | ^nCONFIG
RESERVED | 36 73 | DOUTB4
| 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 _|
\ 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 |
\---------------------------------------------------------------------------
R R A G A R R R V R R D R G R V V E A E G G R D V R R A R G R A R R V R
E E I N I E E E C E E O E N E C C N I N N N E O C E E I E N E I E E C E
S S N D N S S S C S S U S D S C C 0 N 4 D D S U C S S N S D S N S S C S
E E 2 I 2 E E E I E E T E I E I I 5 0 5 I I E T I E E 2 E I E 4 E E I E
R R 5 O 5 R R R O R R M R O R N N M 5 N N R B O R R 5 R O R 5 R R O R
V V M B V V V V V 6 V V T T 4 T T V 7 V V M V V B V V V
E E 2 6 E E E E E E E E E E 5 E E 4 E E E
D D D D D D D D D D D D D D D D D
N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
GNDINT = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
GNDIO = Dedicated ground pin, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
^ = Dedicated configuration pin.
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin.
@ = Special-purpose pin.
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions.
Device-Specific Information: d:\我的文档\zyl\37\s8\xskz.rpt
xskz
** RESOURCE USAGE **
Logic Column Row
Array Interconnect Interconnect Clears/ External
Block Logic Cells Driven Driven Clocks Presets Interconnect
A4 8/ 8(100%) 1/ 8( 12%) 2/ 8( 25%) 0/2 0/2 10/22( 45%)
B17 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 0/2 0/2 11/22( 50%)
B18 8/ 8(100%) 1/ 8( 12%) 3/ 8( 37%) 0/2 0/2 13/22( 59%)
B24 8/ 8(100%) 1/ 8( 12%) 2/ 8( 25%) 0/2 0/2 11/22( 50%)
C2 8/ 8(100%) 1/ 8( 12%) 2/ 8( 25%) 0/2 0/2 14/22( 63%)
C12 8/ 8(100%) 1/ 8( 12%) 3/ 8( 37%) 0/2 0/2 12/22( 54%)
C15 8/ 8(100%) 2/ 8( 25%) 2/ 8( 25%) 0/2 0/2 10/22( 45%)
Embedded Column Row
Array Embedded Interconnect Interconnect Read/ External
Block Cells Driven Driven Clocks Write Interconnect
Total dedicated input pins used: 6/6 (100%)
Total I/O pins used: 54/96 ( 56%)
Total logic cells used: 56/576 ( 9%)
Total embedded cells used: 0/24 ( 0%)
Total EABs used: 0/3 ( 0%)
Average fan-in: 3.42/4 ( 85%)
Total fan-in: 192/2304 ( 8%)
Total input pins required: 44
Total input I/O cell registers required: 0
Total output pins required: 16
Total output I/O cell registers required: 0
Total buried I/O cell registers required: 0
Total bidirectional pins required: 0
Total reserved pins required 0
Total logic cells required: 56
Total flipflops required: 0
Total packed registers required: 0
Total logic cells in carry chains: 0
Total number of carry chains: 0
Total logic cells in cascade chains: 0
Total number of cascade chains: 0
Total single-pin Clock Enables required: 0
Total single-pin Output Enables required: 0
Synthesized logic cells: 0/ 576 ( 0%)
Logic Cell and Embedded Cell Counts
Column: 01 02 03 04 05 06 07 08 09 10 11 12 EA 13 14 15 16 17 18 19 20 21 22 23 24 Total(LC/EC)
A: 0 0 0 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8/0
B: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8 8 0 0 0 0 0 8 24/0
C: 0 8 0 0 0 0 0 0 0 0 0 8 0 0 0 8 0 0 0 0 0 0 0 0 0 24/0
Total: 0 8 0 8 0 0 0 0 0 0 0 8 0 0 0 8 0 8 8 0 0 0 0 0 8 56/0
Device-Specific Information: d:\我的文档\zyl\37\s8\xskz.rpt
xskz
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
95 - - A -- INPUT 0 0 0 1 AIN25B0
86 - - B -- INPUT 0 0 0 1 AIN25B1
131 - - - 15 INPUT 0 0 0 1 AIN25B2
91 - - B -- INPUT 0 0 0 1 AIN25B3
27 - - C -- INPUT 0 0 0 1 AIN25B4
82 - - C -- INPUT 0 0 0 1 AIN25B5
41 - - - 20 INPUT 0 0 0 1 AIN25B6
28 - - C -- INPUT 0 0 0 1 AIN25B7
8 - - A -- INPUT 0 0 0 1 AIN25M0
23 - - B -- INPUT 0 0 0 1 AIN25M1
39 - - - 21 INPUT 0 0 0 1 AIN25M2
90 - - B -- INPUT 0 0 0 1 AIN25M3
32 - - C -- INPUT 0 0 0 1 AIN25M4
64 - - - 10 INPUT 0 0 0 1 AIN25M5
144 - - - 24 INPUT 0 0 0 1 AIN25M6
33 - - C -- INPUT 0 0 0 1 AIN25M7
7 - - A -- INPUT 0 0 0 1 AIN45B0
89 - - B -- INPUT 0 0 0 1 AIN45B1
92 - - B -- INPUT 0 0 0 1 AIN45B2
141 - - - 22 INPUT 0 0 0 1 AIN45B3
68 - - - 07 INPUT 0 0 0 1 AIN45B4
110 - - - 01 INPUT 0 0 0 1 AIN45B5
136 - - - 19 INPUT 0 0 0 1 AIN45B6
29 - - C -- INPUT 0 0 0 1 AIN45B7
9 - - A -- INPUT 0 0 0 1 AIN45M0
128 - - - 13 INPUT 0 0 0 1 AIN45M1
87 - - B -- INPUT 0 0 0 1 AIN45M2
140 - - - 21 INPUT 0 0 0 1 AIN45M3
79 - - C -- INPUT 0 0 0 1 AIN45M4
81 - - C -- INPUT 0 0 0 1 AIN45M5
30 - - C -- INPUT 0 0 0 1 AIN45M6
142 - - - 23 INPUT 0 0 0 1 AIN45M7
98 - - A -- INPUT 0 0 0 3 AIN050
130 - - - 14 INPUT 0 0 0 3 AIN051
88 - - B -- INPUT 0 0 0 3 AIN052
22 - - B -- INPUT 0 0 0 3 AIN053
55 - - - -- INPUT 0 0 0 3 AIN054
112 - - - 03 INPUT 0 0 0 3 AIN055
125 - - - -- INPUT 0 0 0 3 AIN056
31 - - C -- INPUT 0 0 0 3 AIN057
124 - - - -- INPUT 0 0 0 16 EN05B
54 - - - -- INPUT 0 0 0 24 EN05M
126 - - - -- INPUT 0 0 0 16 EN25
56 - - - -- INPUT 0 0 0 16 EN45
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: d:\我的文档\zyl\37\s8\xskz.rpt
xskz
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
96 - - A -- OUTPUT 0 1 0 0 DOUTB0
143 - - - 24 OUTPUT 0 1 0 0 DOUTB1
135 - - - 18 OUTPUT 0 1 0 0 DOUTB2
19 - - B -- OUTPUT 0 1 0 0 DOUTB3
73 - - - 02 OUTPUT 0 1 0 0 DOUTB4
78 - - C -- OUTPUT 0 1 0 0 DOUTB5
17 - - B -- OUTPUT 0 1 0 0 DOUTB6
60 - - - 12 OUTPUT 0 1 0 0 DOUTB7
100 - - A -- OUTPUT 0 1 0 0 DOUTM0
21 - - B -- OUTPUT 0 1 0 0 DOUTM1
20 - - B -- OUTPUT 0 1 0 0 DOUTM2
18 - - B -- OUTPUT 0 1 0 0 DOUTM3
83 - - C -- OUTPUT 0 1 0 0 DOUTM4
80 - - C -- OUTPUT 0 1 0 0 DOUTM5
48 - - - 15 OUTPUT 0 1 0 0 DOUTM6
26 - - C -- OUTPUT 0 1 0 0 DOUTM7
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: d:\我的文档\zyl\37\s8\xskz.rpt
xskz
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 6 - C 15 OR2 2 1 0 1 :530
- 8 - C 15 AND2 2 0 0 2 :543
- 7 - C 15 OR2 3 1 0 1 :544
- 1 - C 15 OR2 2 2 1 1 :548
- 4 - C 15 OR2 2 1 0 1 :554
- 3 - C 15 AND2 2 0 0 2 :561
- 5 - C 15 OR2 3 1 0 1 :562
- 2 - C 15 OR2 2 2 1 1 :563
- 7 - C 12 OR2 2 1 0 1 :569
- 2 - C 12 AND2 2 0 0 2 :576
- 8 - C 12 OR2 3 1 0 1 :577
- 4 - C 12 OR2 2 2 1 1 :578
- 7 - C 02 OR2 2 1 0 1 :584
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