jtdkz.rpt

课程设计《交通灯控制的设计》

-- Equation name is '_LC2_B22', type is buried 
_LC2_B22 = DFFE( _EQ013, GLOBAL( CLK),  VCC,  VCC,  VCC);
  _EQ013 = !STATE0 & !STATE1;

-- Node name is ':9' 
-- Equation name is '_LC1_B22', type is buried 
_LC1_B22 = DFFE(!STATE1, GLOBAL( CLK),  VCC,  VCC,  VCC);

-- Node name is ':11' 
-- Equation name is '_LC6_B22', type is buried 
_LC6_B22 = DFFE( _EQ014, GLOBAL( CLK),  VCC,  VCC,  VCC);
  _EQ014 =  STATE0 &  STATE1;

-- Node name is ':13' 
-- Equation name is '_LC2_B23', type is buried 
_LC2_B23 = DFFE( _EQ015, GLOBAL( CLK),  VCC,  VCC,  VCC);
  _EQ015 = !STATE0 &  STATE1;

-- Node name is '~101~1' 
-- Equation name is '~101~1', location is LC8_B19, type is buried.
-- synthesized logic cell 
_LC8_B19 = LCELL( _EQ016);
  _EQ016 = !S2
         #  S4
         # !S0
         #  S1;

-- Node name is ':101' 
-- Equation name is '_LC1_B14', type is buried 
!_LC1_B14 = _LC1_B14~NOT;
_LC1_B14~NOT = LCELL( _EQ017);
  _EQ017 =  _LC8_B19
         # !S3
         # !S5;

-- Node name is ':317' 
-- Equation name is '_LC8_B13', type is buried 
_LC8_B13 = LCELL( _EQ018);
  _EQ018 = !_LC1_B14 &  _LC5_B19
         #  _LC5_B19 & !SB
         #  _LC1_B14 & !SB;

-- Node name is ':335' 
-- Equation name is '_LC6_B14', type is buried 
_LC6_B14 = LCELL( _EQ019);
  _EQ019 = !_LC1_B14 & !_LC7_B19 &  S3
         # !_LC1_B14 &  _LC7_B19 & !S3
         # !_LC7_B19 & !SB &  S3
         #  _LC7_B19 & !SB & !S3
         #  _LC1_B14 & !SB;

-- Node name is ':344' 
-- Equation name is '_LC4_B13', type is buried 
_LC4_B13 = LCELL( _EQ020);
  _EQ020 = !_LC1_B14 &  _LC3_B19
         #  _LC3_B19 & !SB
         #  _LC1_B14 & !SB;

-- Node name is ':386' 
-- Equation name is '_LC4_B14', type is buried 
!_LC4_B14 = _LC4_B14~NOT;
_LC4_B14~NOT = LCELL( _EQ021);
  _EQ021 =  S3
         #  S5
         #  _LC8_B19;

-- Node name is '~496~1' 
-- Equation name is '~496~1', location is LC1_B19, type is buried.
-- synthesized logic cell 
_LC1_B19 = LCELL( _EQ022);
  _EQ022 =  S5
         #  S2
         # !S4;

-- Node name is ':496' 
-- Equation name is '_LC6_B19', type is buried 
!_LC6_B19 = _LC6_B19~NOT;
_LC6_B19~NOT = LCELL( _EQ023);
  _EQ023 = !S0
         #  S1
         # !S3
         #  _LC1_B19;

-- Node name is ':716' 
-- Equation name is '_LC3_B22', type is buried 
!_LC3_B22 = _LC3_B22~NOT;
_LC3_B22~NOT = LCELL( _EQ024);
  _EQ024 =  STATE1
         # !STATE0;

-- Node name is ':724' 
-- Equation name is '_LC4_B23', type is buried 
_LC4_B23 = LCELL( _EQ025);
  _EQ025 = !STATE0 & !STATE1;

-- Node name is ':808' 
-- Equation name is '_LC7_B23', type is buried 
_LC7_B23 = LCELL( _EQ026);
  _EQ026 =  _LC6_B19 & !STATE0 &  STATE1
         # !_LC4_B14 & !STATE1
         # !_LC4_B14 &  STATE0;

-- Node name is ':820' 
-- Equation name is '_LC7_B13', type is buried 
_LC7_B13 = LCELL( _EQ027);
  _EQ027 = !_LC3_B22 &  _LC5_B19 &  _LC8_B23
         #  _LC3_B22 & !_LC4_B14 &  _LC5_B19;

-- Node name is ':845' 
-- Equation name is '_LC5_B14', type is buried 
_LC5_B14 = LCELL( _EQ028);
  _EQ028 =  _LC3_B22 & !_LC4_B14 & !_LC7_B19 &  S3
         #  _LC3_B22 & !_LC4_B14 &  _LC7_B19 & !S3;

-- Node name is ':846' 
-- Equation name is '_LC3_B14', type is buried 
_LC3_B14 = LCELL( _EQ029);
  _EQ029 = !_LC3_B22 & !_LC7_B19 &  _LC8_B23 &  S3
         # !_LC3_B22 &  _LC7_B19 &  _LC8_B23 & !S3;

-- Node name is ':856' 
-- Equation name is '_LC2_B13', type is buried 
_LC2_B13 = LCELL( _EQ030);
  _EQ030 =  _LC3_B19 & !_LC3_B22 &  _LC8_B23
         #  _LC3_B19 &  _LC3_B22 & !_LC4_B14;

-- Node name is '~865~1' 
-- Equation name is '~865~1', location is LC8_B23, type is buried.
-- synthesized logic cell 
_LC8_B23 = LCELL( _EQ031);
  _EQ031 = !_LC4_B14 & !STATE1
         # !_LC4_B14 &  STATE0
         # !_LC6_B19 & !STATE0 &  STATE1;

-- Node name is '~871~1' 
-- Equation name is '~871~1', location is LC6_B13, type is buried.
-- synthesized logic cell 
_LC6_B13 = LCELL( _EQ032);
  _EQ032 =  _LC3_B22 & !_LC4_B14
         # !_LC3_B22 &  _LC8_B23;

-- Node name is '~871~2' 
-- Equation name is '~871~2', location is LC5_B13, type is buried.
-- synthesized logic cell 
_LC5_B13 = LCELL( _EQ033);
  _EQ033 = !_LC4_B23 &  _LC6_B13
         # !_LC1_B14 &  _LC4_B23;

-- Node name is '~883~1' 
-- Equation name is '~883~1', location is LC6_B23, type is buried.
-- synthesized logic cell 
_LC6_B23 = LCELL( _EQ034);
  _EQ034 =  _LC6_B19 & !STATE0 &  STATE1
         #  _LC4_B14 & !STATE1
         #  _LC4_B14 &  STATE0;



Project Information                            d:\我的文档\zyl\37\s8\jtdkz.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'FLEX10K' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Use Quartus Fitter                        = on
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:01
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:00
   Fitter                                 00:00:01
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:00
   --------------------------             --------
   Total Time                             00:00:02


Memory Allocated
-----------------

Peak memory allocated during compilation  = 15,684K