📄 jtdkz.rpt
字号:
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
22 - - B -- OUTPUT 0 1 0 0 BG0
67 - - B -- OUTPUT 0 1 0 0 BR
24 - - B -- OUTPUT 0 1 0 0 BY0
66 - - B -- OUTPUT 0 1 0 0 MG0
65 - - B -- OUTPUT 0 1 0 0 MR
64 - - B -- OUTPUT 0 1 0 0 MY0
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: d:\我的文档\zyl\37\s8\jtdkz.rpt
jtdkz
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 7 - B 19 OR2 ! 0 3 0 5 |LPM_ADD_SUB:127|addcore:adder|:71
- 3 - B 19 OR2 0 3 0 2 |LPM_ADD_SUB:127|addcore:adder|:92
- 5 - B 19 OR2 0 4 0 2 |LPM_ADD_SUB:127|addcore:adder|:95
- 5 - B 22 DFFE + 0 1 1 0 :3
- 7 - B 22 DFFE + 0 2 1 0 :5
- 2 - B 22 DFFE + 0 2 1 0 :7
- 1 - B 22 DFFE + 0 1 1 0 :9
- 6 - B 22 DFFE + 0 2 1 0 :11
- 2 - B 23 DFFE + 0 2 1 0 :13
- 5 - B 23 DFFE + 0 2 0 11 STATE1 (:15)
- 1 - B 23 DFFE + 1 3 0 10 STATE0 (:16)
- 3 - B 13 DFFE + 0 3 0 4 S5 (:17)
- 2 - B 19 DFFE + 0 3 0 3 S4 (:18)
- 2 - B 14 DFFE + 0 4 0 8 S3 (:19)
- 1 - B 13 DFFE + 0 3 0 4 S2 (:20)
- 4 - B 19 DFFE + 0 2 0 4 S1 (:21)
- 3 - B 23 DFFE + 0 3 0 5 S0 (:22)
- 8 - B 19 OR2 s 0 4 0 2 ~101~1
- 1 - B 14 OR2 ! 0 3 0 6 :101
- 8 - B 13 OR2 1 2 0 1 :317
- 6 - B 14 OR2 1 3 0 1 :335
- 4 - B 13 OR2 1 2 0 1 :344
- 4 - B 14 OR2 ! 0 3 0 8 :386
- 1 - B 19 OR2 s 0 3 0 1 ~496~1
- 6 - B 19 OR2 ! 0 4 0 3 :496
- 3 - B 22 OR2 ! 0 2 0 5 :716
- 4 - B 23 AND2 0 2 0 6 :724
- 7 - B 23 OR2 0 4 0 1 :808
- 7 - B 13 OR2 0 4 0 1 :820
- 5 - B 14 OR2 0 4 0 1 :845
- 3 - B 14 OR2 0 4 0 1 :846
- 2 - B 13 OR2 0 4 0 1 :856
- 8 - B 23 OR2 s 0 4 0 4 ~865~1
- 6 - B 13 OR2 s 0 3 0 1 ~871~1
- 5 - B 13 OR2 s 0 3 0 2 ~871~2
- 6 - B 23 OR2 s 0 4 0 1 ~883~1
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: d:\我的文档\zyl\37\s8\jtdkz.rpt
jtdkz
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
B: 3/ 96( 3%) 0/ 48( 0%) 20/ 48( 41%) 0/16( 0%) 6/16( 37%) 0/16( 0%)
C: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: d:\我的文档\zyl\37\s8\jtdkz.rpt
jtdkz
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 14 CLK
Device-Specific Information: d:\我的文档\zyl\37\s8\jtdkz.rpt
jtdkz
** EQUATIONS **
CLK : INPUT;
SB : INPUT;
-- Node name is 'BG0'
-- Equation name is 'BG0', type is output
BG0 = _LC2_B23;
-- Node name is 'BR'
-- Equation name is 'BR', type is output
BR = _LC1_B22;
-- Node name is 'BY0'
-- Equation name is 'BY0', type is output
BY0 = _LC6_B22;
-- Node name is 'MG0'
-- Equation name is 'MG0', type is output
MG0 = _LC2_B22;
-- Node name is 'MR'
-- Equation name is 'MR', type is output
MR = _LC5_B22;
-- Node name is 'MY0'
-- Equation name is 'MY0', type is output
MY0 = _LC7_B22;
-- Node name is ':16' = 'STATE0'
-- Equation name is 'STATE0', location is LC1_B23, type is buried.
STATE0 = DFFE( _EQ001, GLOBAL( CLK), VCC, VCC, VCC);
_EQ001 = _LC1_B14 & _LC4_B23 & SB
# !_LC4_B23 & _LC7_B23;
-- Node name is ':15' = 'STATE1'
-- Equation name is 'STATE1', location is LC5_B23, type is buried.
STATE1 = DFFE( _EQ002, GLOBAL( CLK), VCC, VCC, VCC);
_EQ002 = _LC4_B14 & STATE0 & !STATE1
# !STATE0 & STATE1
# !_LC4_B14 & STATE1;
-- Node name is ':22' = 'S0'
-- Equation name is 'S0', location is LC3_B23, type is buried.
S0 = DFFE( _EQ003, GLOBAL( CLK), VCC, VCC, VCC);
_EQ003 = _LC1_B14 & _LC4_B23
# !S0
# !_LC4_B23 & _LC6_B23;
-- Node name is ':21' = 'S1'
-- Equation name is 'S1', location is LC4_B19, type is buried.
S1 = DFFE( _EQ004, GLOBAL( CLK), VCC, VCC, VCC);
_EQ004 = _LC5_B13 & !S0 & S1
# _LC5_B13 & S0 & !S1;
-- Node name is ':20' = 'S2'
-- Equation name is 'S2', location is LC1_B13, type is buried.
S2 = DFFE( _EQ005, GLOBAL( CLK), VCC, VCC, VCC);
_EQ005 = _LC2_B13 & !_LC4_B23
# _LC4_B13 & _LC4_B23;
-- Node name is ':19' = 'S3'
-- Equation name is 'S3', location is LC2_B14, type is buried.
S3 = DFFE( _EQ006, GLOBAL( CLK), VCC, VCC, VCC);
_EQ006 = _LC3_B14 & !_LC4_B23
# !_LC4_B23 & _LC5_B14
# _LC4_B23 & _LC6_B14;
-- Node name is ':18' = 'S4'
-- Equation name is 'S4', location is LC2_B19, type is buried.
S4 = DFFE( _EQ007, GLOBAL( CLK), VCC, VCC, VCC);
_EQ007 = _LC5_B13 & _LC7_B19 & S3 & !S4
# _LC5_B13 & !S3 & S4
# _LC5_B13 & !_LC7_B19 & S4;
-- Node name is ':17' = 'S5'
-- Equation name is 'S5', location is LC3_B13, type is buried.
S5 = DFFE( _EQ008, GLOBAL( CLK), VCC, VCC, VCC);
_EQ008 = !_LC4_B23 & _LC7_B13
# _LC4_B23 & _LC8_B13;
-- Node name is '|LPM_ADD_SUB:127|addcore:adder|:71' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC7_B19', type is buried
!_LC7_B19 = _LC7_B19~NOT;
_LC7_B19~NOT = LCELL( _EQ009);
_EQ009 = !S2
# !S0
# !S1;
-- Node name is '|LPM_ADD_SUB:127|addcore:adder|:92' from file "addcore.tdf" line 316, column 45
-- Equation name is '_LC3_B19', type is buried
_LC3_B19 = LCELL( _EQ010);
_EQ010 = !S0 & S2
# !S1 & S2
# S0 & S1 & !S2;
-- Node name is '|LPM_ADD_SUB:127|addcore:adder|:95' from file "addcore.tdf" line 316, column 45
-- Equation name is '_LC5_B19', type is buried
_LC5_B19 = LCELL( _EQ011);
_EQ011 = !S3 & S5
# !_LC7_B19 & S5
# !S4 & S5
# _LC7_B19 & S3 & S4 & !S5;
-- Node name is ':3'
-- Equation name is '_LC5_B22', type is buried
_LC5_B22 = DFFE( STATE1, GLOBAL( CLK), VCC, VCC, VCC);
-- Node name is ':5'
-- Equation name is '_LC7_B22', type is buried
_LC7_B22 = DFFE( _EQ012, GLOBAL( CLK), VCC, VCC, VCC);
_EQ012 = STATE0 & !STATE1;
-- Node name is ':7'
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -