📄 display_8_led.rpt
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_EQ025 = d31 & _LC8_B1
# !_LC8_B1 & num1;
-- Node name is ':432'
-- Equation name is '_LC5_B3', type is buried
_LC5_B3 = LCELL( _EQ026);
_EQ026 = !_LC5_B1 & _LC8_B3
# d21 & _LC5_B1;
-- Node name is ':435'
-- Equation name is '_LC5_B4', type is buried
_LC5_B4 = LCELL( _EQ027);
_EQ027 = !_LC2_B1 & _LC5_B3
# d11 & _LC2_B1;
-- Node name is ':444'
-- Equation name is '_LC6_B11', type is buried
_LC6_B11 = LCELL( _EQ028);
_EQ028 = d30 & _LC8_B1
# !_LC8_B1 & num0;
-- Node name is ':447'
-- Equation name is '_LC7_B11', type is buried
_LC7_B11 = LCELL( _EQ029);
_EQ029 = !_LC5_B1 & _LC6_B11
# d20 & _LC5_B1;
-- Node name is ':450'
-- Equation name is '_LC8_B11', type is buried
_LC8_B11 = LCELL( _EQ030);
_EQ030 = !_LC2_B1 & _LC7_B11
# d10 & _LC2_B1;
-- Node name is '~470~1'
-- Equation name is '~470~1', location is LC6_B4, type is buried.
-- synthesized logic cell
_LC6_B4 = LCELL( _EQ031);
_EQ031 = !_LC1_B1 & !_LC2_B1;
-- Node name is ':595'
-- Equation name is '_LC2_C5', type is buried
_LC2_C5 = LCELL( _EQ032);
_EQ032 = !num0 & !num1 & !num2 & !num3;
-- Node name is ':600'
-- Equation name is '_LC4_C5', type is buried
!_LC4_C5 = _LC4_C5~NOT;
_LC4_C5~NOT = LCELL( _EQ033);
_EQ033 = num1
# !num0
# num3
# num2;
-- Node name is ':605'
-- Equation name is '_LC3_C5', type is buried
_LC3_C5 = LCELL( _EQ034);
_EQ034 = !num0 & num1 & !num2 & !num3;
-- Node name is ':610'
-- Equation name is '_LC7_C5', type is buried
!_LC7_C5 = _LC7_C5~NOT;
_LC7_C5~NOT = LCELL( _EQ035);
_EQ035 = !num1
# !num0
# num3
# num2;
-- Node name is ':615'
-- Equation name is '_LC5_C5', type is buried
!_LC5_C5 = _LC5_C5~NOT;
_LC5_C5~NOT = LCELL( _EQ036);
_EQ036 = num1
# num0
# num3
# !num2;
-- Node name is ':620'
-- Equation name is '_LC6_C5', type is buried
!_LC6_C5 = _LC6_C5~NOT;
_LC6_C5~NOT = LCELL( _EQ037);
_EQ037 = num1
# !num0
# num3
# !num2;
-- Node name is ':625'
-- Equation name is '_LC2_C8', type is buried
_LC2_C8 = LCELL( _EQ038);
_EQ038 = !num0 & num1 & num2 & !num3;
-- Node name is ':630'
-- Equation name is '_LC4_C8', type is buried
!_LC4_C8 = _LC4_C8~NOT;
_LC4_C8~NOT = LCELL( _EQ039);
_EQ039 = !num1
# !num0
# num3
# !num2;
-- Node name is ':635'
-- Equation name is '_LC3_C8', type is buried
_LC3_C8 = LCELL( _EQ040);
_EQ040 = !num0 & !num1 & !num2 & num3;
-- Node name is ':640'
-- Equation name is '_LC6_C8', type is buried
!_LC6_C8 = _LC6_C8~NOT;
_LC6_C8~NOT = LCELL( _EQ041);
_EQ041 = num1
# !num0
# !num3
# num2;
-- Node name is ':776'
-- Equation name is '_LC2_A1', type is buried
_LC2_A1 = LCELL( _EQ042);
_EQ042 = num1 & num3
# num1 & !num2
# !num0 & num1
# !num2 & num3
# num0 & num3
# !num0 & num2 & !num3
# num0 & !num1 & num2;
-- Node name is ':825'
-- Equation name is '_LC7_A1', type is buried
_LC7_A1 = LCELL( _EQ043);
_EQ043 = !num2 & num3
# !num0 & num3
# num1 & num3
# !num0 & !num1
# !num1 & num2 & !num3
# !num0 & num2;
-- Node name is '~846~1'
-- Equation name is '~846~1', location is LC5_C8, type is buried.
-- synthesized logic cell
_LC5_C8 = LCELL( _EQ044);
_EQ044 = num0 & num1 & num2 & num3
# !num0 & num1 & !num2 & num3;
-- Node name is ':854'
-- Equation name is '_LC8_C8', type is buried
_LC8_C8 = LCELL( _EQ045);
_EQ045 = _LC5_C8 & !_LC6_C8
# !_LC6_C8 & _LC7_C8;
-- Node name is ':858'
-- Equation name is '_LC1_C8', type is buried
_LC1_C8 = LCELL( _EQ046);
_EQ046 = _LC2_C8
# _LC3_C8 & !_LC4_C8
# !_LC4_C8 & _LC8_C8;
-- Node name is ':872'
-- Equation name is '_LC8_C5', type is buried
_LC8_C5 = LCELL( _EQ047);
_EQ047 = _LC1_C8 & !_LC5_C5 & !_LC6_C5 & !_LC7_C5;
-- Node name is ':876'
-- Equation name is '_LC1_C5', type is buried
_LC1_C5 = LCELL( _EQ048);
_EQ048 = _LC2_C5
# _LC3_C5 & !_LC4_C5
# !_LC4_C5 & _LC8_C5;
-- Node name is ':894'
-- Equation name is '_LC7_C8', type is buried
_LC7_C8 = LCELL( _EQ049);
_EQ049 = num0 & num1 & !num2 & num3
# !num1 & num2 & num3
# !num0 & num2 & num3;
-- Node name is ':927'
-- Equation name is '_LC3_A1', type is buried
_LC3_A1 = LCELL( _EQ050);
_EQ050 = num1 & !num2 & !num3
# !num0 & !num2 & !num3
# !num0 & num1 & !num3
# !num0 & !num1 & !num2
# !num1 & !num2 & num3
# num0 & num1 & !num2
# !num0 & !num1 & num3
# num0 & !num1 & num2
# !num0 & num1 & num2;
-- Node name is ':978'
-- Equation name is '_LC8_A1', type is buried
_LC8_A1 = LCELL( _EQ051);
_EQ051 = !num1 & !num3
# num2 & !num3
# num0 & !num1
# !num2 & num3
# !num1 & !num2
# num0 & !num2
# num0 & !num3;
-- Node name is ':1029'
-- Equation name is '_LC1_A1', type is buried
_LC1_A1 = LCELL( _EQ052);
_EQ052 = !num2 & !num3
# !num0 & !num1 & !num3
# num0 & !num1 & num3
# !num0 & !num2
# !num1 & !num2
# num0 & num1 & !num3;
-- Node name is ':1080'
-- Equation name is '_LC5_A1', type is buried
_LC5_A1 = LCELL( _EQ053);
_EQ053 = !num0 & !num2
# !num1 & !num2 & num3
# num0 & num2 & !num3
# num1 & !num3
# !num0 & num3
# !num0 & num1
# num1 & num2;
Project Information d:\我的文档\zyl\37\s8\display_8_led.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:01
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:01
Memory Allocated
-----------------
Peak memory allocated during compilation = 15,307K
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