📄 display_8_led.rpt
字号:
- 6 - B 04 AND2 s 0 2 0 1 ~470~1
- 2 - C 05 AND2 0 4 0 1 :595
- 4 - C 05 OR2 ! 0 4 0 1 :600
- 3 - C 05 AND2 0 4 0 1 :605
- 7 - C 05 OR2 ! 0 4 0 1 :610
- 5 - C 05 OR2 ! 0 4 0 1 :615
- 6 - C 05 OR2 ! 0 4 0 1 :620
- 2 - C 08 AND2 0 4 0 1 :625
- 4 - C 08 OR2 ! 0 4 0 1 :630
- 3 - C 08 AND2 0 4 0 1 :635
- 6 - C 08 OR2 ! 0 4 0 1 :640
- 2 - A 01 OR2 0 4 1 0 :776
- 7 - A 01 OR2 0 4 1 0 :825
- 5 - C 08 OR2 s 0 4 0 1 ~846~1
- 8 - C 08 OR2 0 3 0 1 :854
- 1 - C 08 OR2 0 4 0 1 :858
- 8 - C 05 AND2 0 4 0 1 :872
- 1 - C 05 OR2 0 4 1 0 :876
- 7 - C 08 OR2 0 4 0 1 :894
- 3 - A 01 OR2 0 4 1 0 :927
- 8 - A 01 OR2 0 4 1 0 :978
- 1 - A 01 OR2 0 4 1 0 :1029
- 5 - A 01 OR2 0 4 1 0 :1080
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: d:\我的文档\zyl\37\s8\display_8_led.rpt
display_8_led
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 2/ 96( 2%) 7/ 48( 14%) 0/ 48( 0%) 0/16( 0%) 5/16( 31%) 0/16( 0%)
B: 9/ 96( 9%) 15/ 48( 31%) 0/ 48( 0%) 7/16( 43%) 2/16( 12%) 0/16( 0%)
C: 1/ 96( 1%) 5/ 48( 10%) 0/ 48( 0%) 0/16( 0%) 1/16( 6%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 2/24( 8%) 1/4( 25%) 1/4( 25%) 0/4( 0%)
02: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
03: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 3/24( 12%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: d:\我的文档\zyl\37\s8\display_8_led.rpt
display_8_led
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 13 clk
Device-Specific Information: d:\我的文档\zyl\37\s8\display_8_led.rpt
display_8_led
** EQUATIONS **
clk : INPUT;
d00 : INPUT;
d01 : INPUT;
d02 : INPUT;
d03 : INPUT;
d10 : INPUT;
d11 : INPUT;
d12 : INPUT;
d13 : INPUT;
d20 : INPUT;
d21 : INPUT;
d22 : INPUT;
d23 : INPUT;
d30 : INPUT;
d31 : INPUT;
d32 : INPUT;
d33 : INPUT;
-- Node name is 'led0'
-- Equation name is 'led0', type is output
led0 = _LC5_A1;
-- Node name is 'led1'
-- Equation name is 'led1', type is output
led1 = _LC1_A1;
-- Node name is 'led2'
-- Equation name is 'led2', type is output
led2 = _LC8_A1;
-- Node name is 'led3'
-- Equation name is 'led3', type is output
led3 = _LC3_A1;
-- Node name is 'led4'
-- Equation name is 'led4', type is output
led4 = _LC1_C5;
-- Node name is 'led5'
-- Equation name is 'led5', type is output
led5 = _LC7_A1;
-- Node name is 'led6'
-- Equation name is 'led6', type is output
led6 = _LC2_A1;
-- Node name is ':43' = 'num0'
-- Equation name is 'num0', location is LC1_B11, type is buried.
num0 = DFFE( _EQ001, GLOBAL( clk), VCC, VCC, VCC);
_EQ001 = !_LC1_B1 & _LC8_B11
# d00 & _LC1_B1;
-- Node name is ':42' = 'num1'
-- Equation name is 'num1', location is LC1_B4, type is buried.
num1 = DFFE( _EQ002, GLOBAL( clk), VCC, VCC, VCC);
_EQ002 = !_LC1_B1 & _LC5_B4
# d01 & _LC1_B1;
-- Node name is ':41' = 'num2'
-- Equation name is 'num2', location is LC4_B11, type is buried.
num2 = DFFE( _EQ003, GLOBAL( clk), VCC, VCC, VCC);
_EQ003 = !_LC1_B1 & _LC5_B11
# d02 & _LC1_B1;
-- Node name is ':40' = 'num3'
-- Equation name is 'num3', location is LC7_B4, type is buried.
num3 = DFFE( _EQ004, GLOBAL( clk), VCC, VCC, VCC);
_EQ004 = !_LC1_B1 & _LC4_B4
# d03 & _LC1_B1;
-- Node name is ':36' = 'q0'
-- Equation name is 'q0', location is LC4_B3, type is buried.
q0 = DFFE(!q0, GLOBAL( clk), VCC, VCC, VCC);
-- Node name is ':35' = 'q1'
-- Equation name is 'q1', location is LC7_B3, type is buried.
q1 = DFFE( _EQ005, GLOBAL( clk), VCC, VCC, VCC);
_EQ005 = !_LC7_B1 & q0 & !q1
# !_LC7_B1 & !q0 & q1;
-- Node name is ':34' = 'q2'
-- Equation name is 'q2', location is LC3_B3, type is buried.
q2 = DFFE( _EQ006, GLOBAL( clk), VCC, VCC, VCC);
_EQ006 = !_LC7_B1 & !q0 & q2
# !_LC7_B1 & !q1 & q2
# !_LC7_B1 & q0 & q1 & !q2;
-- Node name is ':33' = 'q3'
-- Equation name is 'q3', location is LC2_B3, type is buried.
q3 = DFFE( _EQ007, GLOBAL( clk), VCC, VCC, VCC);
_EQ007 = !_LC1_B3 & !_LC7_B1 & q3
# _LC1_B3 & !_LC7_B1 & !q3;
-- Node name is ':32' = 'q4'
-- Equation name is 'q4', location is LC3_B1, type is buried.
q4 = DFFE( _EQ008, GLOBAL( clk), VCC, VCC, VCC);
_EQ008 = !q3 & q4
# !_LC1_B3 & q4
# _LC1_B3 & q3 & !q4;
-- Node name is ':31' = 'q5'
-- Equation name is 'q5', location is LC6_B1, type is buried.
q5 = DFFE( _EQ009, GLOBAL( clk), VCC, VCC, VCC);
_EQ009 = !q4 & q5
# !q3 & q5
# !_LC1_B3 & q5
# _LC1_B3 & q3 & q4 & !q5;
-- Node name is 'sel0'
-- Equation name is 'sel0', type is output
sel0 = _LC6_B3;
-- Node name is 'sel1'
-- Equation name is 'sel1', type is output
sel1 = _LC4_B1;
-- Node name is 'sel2'
-- Equation name is 'sel2', type is output
sel2 = _LC8_B4;
-- Node name is '|LPM_ADD_SUB:106|addcore:adder|:67' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC1_B3', type is buried
!_LC1_B3 = _LC1_B3~NOT;
_LC1_B3~NOT = LCELL( _EQ010);
_EQ010 = !q2
# !q0
# !q1;
-- Node name is ':25'
-- Equation name is '_LC8_B4', type is buried
_LC8_B4 = DFFE( _EQ011, GLOBAL( clk), VCC, VCC, VCC);
_EQ011 = !_LC5_B1 & _LC6_B4 & !_LC8_B1 & _LC8_B4;
-- Node name is ':27'
-- Equation name is '_LC4_B1', type is buried
_LC4_B1 = DFFE( _EQ012, GLOBAL( clk), VCC, VCC, VCC);
_EQ012 = q4 & !q5
# _LC4_B1 & q5
# _LC4_B1 & q4;
-- Node name is ':29'
-- Equation name is '_LC6_B3', type is buried
_LC6_B3 = DFFE( _EQ013, GLOBAL( clk), VCC, VCC, VCC);
_EQ013 = q3 & !q5
# _LC6_B3 & q5
# _LC6_B3 & q3;
-- Node name is ':69'
-- Equation name is '_LC7_B1', type is buried
!_LC7_B1 = _LC7_B1~NOT;
_LC7_B1~NOT = LCELL( _EQ014);
_EQ014 = !q5
# !q4
# !q3
# !_LC1_B3;
-- Node name is ':268'
-- Equation name is '_LC1_B1', type is buried
_LC1_B1 = LCELL( _EQ015);
_EQ015 = !q3 & !q4 & !q5;
-- Node name is ':275'
-- Equation name is '_LC2_B1', type is buried
_LC2_B1 = LCELL( _EQ016);
_EQ016 = q3 & !q4 & !q5;
-- Node name is ':282'
-- Equation name is '_LC5_B1', type is buried
_LC5_B1 = LCELL( _EQ017);
_EQ017 = !q3 & q4 & !q5;
-- Node name is ':289'
-- Equation name is '_LC8_B1', type is buried
!_LC8_B1 = _LC8_B1~NOT;
_LC8_B1~NOT = LCELL( _EQ018);
_EQ018 = q5
# !q3
# !q4;
-- Node name is ':390'
-- Equation name is '_LC2_B4', type is buried
_LC2_B4 = LCELL( _EQ019);
_EQ019 = d33 & _LC8_B1
# !_LC8_B1 & num3;
-- Node name is ':396'
-- Equation name is '_LC3_B4', type is buried
_LC3_B4 = LCELL( _EQ020);
_EQ020 = _LC2_B4 & !_LC5_B1
# d23 & _LC5_B1;
-- Node name is ':402'
-- Equation name is '_LC4_B4', type is buried
_LC4_B4 = LCELL( _EQ021);
_EQ021 = !_LC2_B1 & _LC3_B4
# d13 & _LC2_B1;
-- Node name is ':414'
-- Equation name is '_LC2_B11', type is buried
_LC2_B11 = LCELL( _EQ022);
_EQ022 = d32 & _LC8_B1
# !_LC8_B1 & num2;
-- Node name is ':417'
-- Equation name is '_LC3_B11', type is buried
_LC3_B11 = LCELL( _EQ023);
_EQ023 = _LC2_B11 & !_LC5_B1
# d22 & _LC5_B1;
-- Node name is ':420'
-- Equation name is '_LC5_B11', type is buried
_LC5_B11 = LCELL( _EQ024);
_EQ024 = !_LC2_B1 & _LC3_B11
# d12 & _LC2_B1;
-- Node name is ':429'
-- Equation name is '_LC8_B3', type is buried
_LC8_B3 = LCELL( _EQ025);
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