📄 cnt25s.rpt
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Project Information d:\我的文档\zyl\37\s8\cnt25s.rpt
MAX+plus II Compiler Report File
Version 10.2 07/10/2002
Compiled: 12/27/2007 13:23:58
Copyright (C) 1988-2002 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera. Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
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limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner. Title to
the intellectual property, including patents, copyrights, trademarks,
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***** Project compilation was successful
CNT25S
** DEVICE SUMMARY **
Chip/ Input Output Bidir Memory Memory LCs
POF Device Pins Pins Pins Bits % Utilized LCs % Utilized
cnt25s EPF10K10LC84-3 2 16 0 0 0 % 107 18 %
User Pins: 2 16 0
Project Information d:\我的文档\zyl\37\s8\cnt25s.rpt
** FILE HIERARCHY **
|lpm_add_sub:88|
|lpm_add_sub:88|addcore:adder|
|lpm_add_sub:88|altshift:result_ext_latency_ffs|
|lpm_add_sub:88|altshift:carry_ext_latency_ffs|
|lpm_add_sub:88|altshift:oflow_ext_latency_ffs|
|lpm_add_sub:130|
|lpm_add_sub:130|addcore:adder|
|lpm_add_sub:130|altshift:result_ext_latency_ffs|
|lpm_add_sub:130|altshift:carry_ext_latency_ffs|
|lpm_add_sub:130|altshift:oflow_ext_latency_ffs|
|lpm_add_sub:131|
|lpm_add_sub:131|addcore:adder|
|lpm_add_sub:131|altshift:result_ext_latency_ffs|
|lpm_add_sub:131|altshift:carry_ext_latency_ffs|
|lpm_add_sub:131|altshift:oflow_ext_latency_ffs|
Device-Specific Information: d:\我的文档\zyl\37\s8\cnt25s.rpt
cnt25s
***** Logic for device 'cnt25s' compiled without errors.
Device: EPF10K10LC84-3
FLEX 10K Configuration Scheme: Passive Serial
Device Options:
User-Supplied Start-Up Clock = OFF
Auto-Restart Configuration on Frame Error = OFF
Release Clears Before Tri-States = OFF
Enable Chip_Wide Reset = OFF
Enable Chip-Wide Output Enable = OFF
Enable INIT_DONE Output = OFF
JTAG User Code = 7f
^
C
D R R R D R R R R R R R R O
O E E E O E E E E E E E E N
U S S S U S S V S G S G S S S S F
T E E E T E E C E N E N E E E E _ ^
2 R R R 2 R R C R E D R D R R R R # D n
5 V V V 5 V V I V N C I V I V V V V T O C
M E E E B E E N E 2 L N E N E E E E C N E
6 D D D 7 D D T D 5 K T D T D D D D K E O
-----------------------------------------------------------------_
/ 11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75 |
^DATA0 | 12 74 | #TDO
^DCLK | 13 73 | RESERVED
^nCE | 14 72 | RESERVED
#TDI | 15 71 | RESERVED
DOUT25M7 | 16 70 | RESERVED
RESERVED | 17 69 | RESERVED
RESERVED | 18 68 | GNDINT
RESERVED | 19 67 | DOUT25B5
VCCINT | 20 66 | DOUT25M5
DOUT25B1 | 21 65 | DOUT25M3
DOUT25B4 | 22 EPF10K10LC84-3 64 | DOUT25M1
DOUT25B3 | 23 63 | VCCINT
DOUT25M0 | 24 62 | RESERVED
DOUT25B2 | 25 61 | RESERVED
GNDINT | 26 60 | DOUT25B6
RESERVED | 27 59 | RESERVED
RESERVED | 28 58 | RESERVED
RESERVED | 29 57 | #TMS
RESERVED | 30 56 | #TRST
^MSEL0 | 31 55 | ^nSTATUS
^MSEL1 | 32 54 | RESERVED
|_ 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 _|
------------------------------------------------------------------
V ^ R R R R R V G G G G V G D R R D R D R
C n E E E E E C N N N N C N O E E O E O E
C C S S S S S C D D D D C D U S S U S U S
I O E E E E E I I I I I I I T E E T E T E
N N R R R R R N N N N N N N 2 R R 2 R 2 R
T F V V V V V T T T T T T T 5 V V 5 V 5 V
I E E E E E B E E M E M E
G D D D D D 0 D D 2 D 4 D
N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
GNDINT = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
GNDIO = Dedicated ground pin, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
^ = Dedicated configuration pin.
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin.
@ = Special-purpose pin.
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions.
Device-Specific Information: d:\我的文档\zyl\37\s8\cnt25s.rpt
cnt25s
** RESOURCE USAGE **
Logic Column Row
Array Interconnect Interconnect Clears/ External
Block Logic Cells Driven Driven Clocks Presets Interconnect
B2 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 2/22( 9%)
B4 8/ 8(100%) 0/ 8( 0%) 7/ 8( 87%) 0/2 0/2 5/22( 22%)
B10 8/ 8(100%) 0/ 8( 0%) 6/ 8( 75%) 1/2 0/2 3/22( 13%)
B11 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 2/22( 9%)
B13 8/ 8(100%) 0/ 8( 0%) 6/ 8( 75%) 0/2 0/2 8/22( 36%)
B14 8/ 8(100%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 17/22( 77%)
B15 8/ 8(100%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 17/22( 77%)
B16 8/ 8(100%) 0/ 8( 0%) 7/ 8( 87%) 0/2 0/2 8/22( 36%)
B17 8/ 8(100%) 0/ 8( 0%) 7/ 8( 87%) 0/2 0/2 8/22( 36%)
B18 8/ 8(100%) 1/ 8( 12%) 1/ 8( 12%) 0/2 0/2 16/22( 72%)
B19 8/ 8(100%) 1/ 8( 12%) 3/ 8( 37%) 0/2 0/2 10/22( 45%)
B20 8/ 8(100%) 0/ 8( 0%) 2/ 8( 25%) 0/2 0/2 16/22( 72%)
B21 7/ 8( 87%) 0/ 8( 0%) 7/ 8( 87%) 0/2 0/2 4/22( 18%)
B22 8/ 8(100%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 19/22( 86%)
B23 2/ 8( 25%) 0/ 8( 0%) 2/ 8( 25%) 0/2 0/2 4/22( 18%)
B24 8/ 8(100%) 0/ 8( 0%) 6/ 8( 75%) 0/2 0/2 10/22( 45%)
Embedded Column Row
Array Embedded Interconnect Interconnect Read/ External
Block Cells Driven Driven Clocks Write Interconnect
Total dedicated input pins used: 2/6 ( 33%)
Total I/O pins used: 16/53 ( 30%)
Total logic cells used: 107/576 ( 18%)
Total embedded cells used: 0/24 ( 0%)
Total EABs used: 0/3 ( 0%)
Average fan-in: 3.48/4 ( 87%)
Total fan-in: 373/2304 ( 16%)
Total input pins required: 2
Total input I/O cell registers required: 0
Total output pins required: 16
Total output I/O cell registers required: 0
Total buried I/O cell registers required: 0
Total bidirectional pins required: 0
Total reserved pins required 0
Total logic cells required: 107
Total flipflops required: 5
Total packed registers required: 0
Total logic cells in carry chains: 0
Total number of carry chains: 0
Total logic cells in cascade chains: 0
Total number of cascade chains: 0
Total single-pin Clock Enables required: 0
Total single-pin Output Enables required: 0
Synthesized logic cells: 37/ 576 ( 6%)
Logic Cell and Embedded Cell Counts
Column: 01 02 03 04 05 06 07 08 09 10 11 12 EA 13 14 15 16 17 18 19 20 21 22 23 24 Total(LC/EC)
A: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
B: 0 1 0 8 0 0 0 0 0 8 1 0 0 8 8 8 8 8 8 8 8 7 8 2 8 107/0
C: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
Total: 0 1 0 8 0 0 0 0 0 8 1 0 0 8 8 8 8 8 8 8 8 7 8 2 8 107/0
Device-Specific Information: d:\我的文档\zyl\37\s8\cnt25s.rpt
cnt25s
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
1 - - - -- INPUT G 0 0 0 0 CLK
2 - - - -- INPUT 0 0 0 5 EN25
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: d:\我的文档\zyl\37\s8\cnt25s.rpt
cnt25s
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
47 - - - 14 OUTPUT 0 1 0 0 DOUT25B0
21 - - B -- OUTPUT 0 1 0 0 DOUT25B1
25 - - B -- OUTPUT 0 1 0 0 DOUT25B2
23 - - B -- OUTPUT 0 1 0 0 DOUT25B3
22 - - B -- OUTPUT 0 1 0 0 DOUT25B4
67 - - B -- OUTPUT 0 1 0 0 DOUT25B5
60 - - C -- OUTPUT 0 0 0 0 DOUT25B6
7 - - - 03 OUTPUT 0 0 0 0 DOUT25B7
24 - - B -- OUTPUT 0 1 0 0 DOUT25M0
64 - - B -- OUTPUT 0 1 0 0 DOUT25M1
50 - - - 17 OUTPUT 0 1 0 0 DOUT25M2
65 - - B -- OUTPUT 0 1 0 0 DOUT25M3
52 - - - 19 OUTPUT 0 1 0 0 DOUT25M4
66 - - B -- OUTPUT 0 1 0 0 DOUT25M5
11 - - - 01 OUTPUT 0 0 0 0 DOUT25M6
16 - - A -- OUTPUT 0 0 0 0 DOUT25M7
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: d:\我的文档\zyl\37\s8\cnt25s.rpt
cnt25s
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 2 - B 04 AND2 0 2 0 9 |LPM_ADD_SUB:88|addcore:adder|:59
- 7 - B 10 AND2 0 2 0 1 |LPM_ADD_SUB:88|addcore:adder|:63
- 4 - B 21 AND2 0 3 0 1 |LPM_ADD_SUB:88|addcore:adder|:67
- 8 - B 10 DFFE + 1 2 0 26 CNT5B4 (:19)
- 6 - B 10 DFFE + 1 2 0 15 CNT5B3 (:20)
- 3 - B 10 DFFE + 1 2 0 47 CNT5B2 (:21)
- 2 - B 10 DFFE + 1 2 0 9 CNT5B1 (:22)
- 1 - B 10 DFFE + 1 1 0 10 CNT5B0 (:23)
- 5 - B 10 OR2 s 0 2 0 1 ~54~1
- 4 - B 10 OR2 ! 0 4 0 8 :54
- 5 - B 21 AND2 0 4 0 4 :1548
- 1 - B 17 AND2 0 3 0 5 :1562
- 7 - B 16 OR2 s ! 0 3 0 3 ~1576~1
- 1 - B 16 OR2 ! 0 2 0 6 :1576
- 2 - B 02 AND2 0 2 0 6 :1590
- 1 - B 21 OR2 ! 0 4 0 6 :1604
- 4 - B 17 AND2 0 3 0 6 :1618
- 3 - B 16 OR2 ! 0 3 0 6 :1632
- 1 - B 04 AND2 0 3 0 6 :1646
- 2 - B 21 OR2 ! 0 4 0 5 :1660
- 6 - B 17 AND2 0 2 0 4 :1674
- 3 - B 21 OR2 ! 0 4 0 5 :1716
- 4 - B 04 AND2 s 0 4 0 6 ~1730~1
- 7 - B 17 OR2 s ! 0 4 0 9 ~1744~1
- 3 - B 04 AND2 s 0 4 0 11 ~1758~1
- 8 - B 21 OR2 ! 0 4 0 7 :1772
- 6 - B 04 AND2 s 0 4 0 12 ~1786~1
- 4 - B 16 OR2 s ! 0 2 0 5 ~1800~1
- 8 - B 04 AND2 s 0 3 0 3 ~1814~1
- 5 - B 04 AND2 s 0 2 0 7 ~1814~2
- 6 - B 21 OR2 ! 0 4 0 6 :1828
- 8 - B 17 AND2 s 0 3 0 2 ~1842~1
- 8 - B 16 OR2 ! 0 3 0 4 :1856
- 7 - B 04 AND2 0 3 0 7 :1870
- 4 - B 19 OR2 s 0 3 0 4 ~2029~1
- 1 - B 19 OR2 0 3 1 2 :2029
- 5 - B 17 OR2 s ! 0 4 0 5 ~2089~1
- 6 - B 24 OR2 s 0 3 0 2 ~2089~2
- 8 - B 24 AND2 s ! 0 2 0 1 ~2089~3
- 2 - B 24 OR2 0 4 1 0 :2109
- 1 - B 23 AND2 ! 0 2 0 3 :2137
- 3 - B 24 OR2 0 4 1 0 :2187
- 4 - B 13 OR2 0 4 0 2 :2209
- 2 - B 18 OR2 0 4 0 1 :2232
- 3 - B 17 OR2 s 0 3 0 4 ~2239~1
- 4 - B 24 OR2 s 0 4 0 1 ~2239~2
- 3 - B 18 OR2 s 0 4 0 1 ~2262~1
- 8 - B 18 OR2 0 4 1 0 :2263
- 8 - B 13 OR2 0 4 0 1 :2286
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