speaker.cmd

dsp各模块相结合

-l rts2xx.lib
MEMORY
{
    PAGE 0 :   VECS   : origin =    0h , length =   040h   /* VECTORS */
	       PROG   : origin =   40h , length = 0FFC0h   /* PROGRAM */
	       /*PRCT   : origin =   40  , length  =0FFC0h
	       PROG   : origin = 9000h   ,length=2000h*/
	
    PAGE 1 :   /*IDATA1 :o=300h,length=100h*/
	       /*IDATA2 : origin = 0c00h , length =   400h*/
	       MMRS   : origin =    0h , length =   060h   /* MMRS    */
           B2     : origin = 0060h , length =   020h   /* DARAM   */
           B0     : origin = 0200h , length =  0100h   /* DARAM   */
           B1     : origin = 0300h , length =  0100h   /* DARAM   */
           IDATA2 : origin = 0c00h , length =   400h
	       REG_MEM: origin = 7000h , length =  1000h
	       DATA   : origin = 8000h , length =  8000h   /* XDM     */
}

/*--------------------------------------------------------------------*/
/* SECTIONS ALLOCATION                                                */
/*--------------------------------------------------------------------*/
SECTIONS
{
    .vectors : { } > VECS      PAGE 0   /* Interrupt vector table     */
    /*.prct    : { } > PRCT      PAGE 0  */
    .text    : { } > PROG      PAGE 0   /* Code                       */
    .cinit   : { } > PROG      PAGE 0 
    .data    : { } > PROG      PAGE 0   /* Initialization data tables */
    .mmrs    : { } > MMRS      PAGE 1   /* Memory mapped registers    */
    .bss     : { } > DATA      PAGE 1   /* Block B2                   */
    .blk0    : { } > B0        PAGE 1   /* Block B0                   */
    .blk1    : { } > B1        PAGE 1   /* Block B1                   */
    .blk2    : { } > B2        PAGE 1   /* Block B2                   */
    .stack   : { } > IDATA2    PAGE 1
    .reg240x : { } > REG_MEM   PAGE 1
    .blk3    : { } > DATA      PAGE 1   /* External data memory       */
}