top.vhd

波特率发生器

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity top is
    Port (clk32mhz,reset,rxd,xmit_cmd_p_in:in std_logic;    --总的输入输出信号的定义
	     rec_ready,txd_out,txd_done_out:out std_logic; 
txdbuf_in:in std_logic_vector(7 downto 0);         --待发送数据输入
	   	 rec_buf:out std_logic_vector(7 downto 0));		    --接收数据缓冲
end top;
architecture Behavioral of top is

component reciever
    Port (bclkr,resetr,rxdr:in std_logic;
	     r_ready:out std_logic;
		 rbuf:out std_logic_vector(7 downto 0));
end component;

component transfer
    Port (bclkt,resett,xmit_cmd_p:in std_logic;
	     txdbuf:in std_logic_vector(7 downto 0);
		 txd:out std_logic;
		 txd_done:out std_logic);
end component;

component baud
    Port (clk,resetb:in std_logic;
	     bclk:out std_logic);
end component;

signal b:std_logic;
begin
u1:baud port map(clk=>clk32mhz,resetb=>reset,bclk=>b);             --顶层映射
u2:reciever port map(bclkr=>b,resetr=>reset,rxdr=>rxd,r_ready=>rec_ready,
                     rbuf=>rec_buf);
u3:transfer port map(bclkt=>b,resett=>reset,xmit_cmd_p=>xmit_cmd_p_in,
                     txdbuf=>txdbuf_in,txd=>txd_out,txd_done=>txd_done_out);
end Behavioral;