pcf8574a.c

这是一个有关C8051F020单片机的实验教学材料,相信对于单片机的研究人员会有很大的帮助.

//-----------------------------------------------------------------------------
// Includes
//-----------------------------------------------------------------------------
#include <c8051f020.h>                    // SFR declarations
#include <intrins.h>
//------------------------------------------------------------------------------------
// Global CONSTANTS
//------------------------------------------------------------------------------------

#define  WRITE       0x00                 // WRITE direction bit
#define  READ        0x01                 // READ direction bit

#define  CHIP_B      0x70

#define  SMB_START      0x08              // (MT & MR) START transmitted
#define  SMB_RP_START   0x10              // (MT & MR) repeated START
#define  SMB_MTADDACK   0x18              // (MT) Slave address + W transmitted;
                                          //  ACK received
#define  SMB_MTDBACK    0x28              // (MT) data byte transmitted; ACK rec'vd
#define  SMB_MRADDACK   0x40              // (MR) Slave address + R transmitted;
                                          //  ACK received
#define  SMB_MRDBNACK   0x58              // (MR) data byte rec'vd; NACK transmitted
//-----------------------------------------------------------------------------------
//Global VARIABLES
//-----------------------------------------------------------------------------------

char COMMAND;                             // Holds the slave address + R/W bit for
char COMMAND1;                                          // use in the SMBus ISR.

char WORD;                                // Holds data to be transmitted by the SMBus
unsigned char xdata SENDMODE;                                         // that has just been received.



bit SM_BUSY;                              // This bit is set when a send or receive
                                          // is started. It is cleared by the
                                          // ISR when the operation is finished.

//------------------------------------------------------------------------------------
// Function PROTOTYPES
//------------------------------------------------------------------------------------
void SYSCLK_Init (void);
char SLA_READ(char chip_select);
void SLA_SEND(char chip_select, char wr_data);
//------------------------------------------------------------------------------------
// MAIN Routine
//------------------------------------------------------------------------------------
void sleep_ms(unsigned int count)
{
  unsigned char ii,jj;
  for(ii=0;ii<count;ii++)
    {
      for(jj=0;jj<250;jj++)
	  _nop_();			
    }	
}


void MAIN (void)
{
	unsigned char i,temp;
   WDTCN = 0xde;                          // disable watchdog timer
   WDTCN = 0xad;
   SYSCLK_Init();                         // turn on the external oscillator
   XBR0 = 0x07;                           // Route SMBus to GPIO pins through crossbar
   XBR2 = 0x40;                           // Enable crossbar and weak pull-ups
   SMB0CN = 0x44;                         // Enable SMBus with acknowledge low (AA = 1)
   SMB0CR = -80;                          // SMBus clock rate = 100 kHz
   EIE1 |= 2;                             // SMBus interrupt enable
   EA = 1;                                // Global interrupt enable
   SM_BUSY = 0;                           // Free bus for first transfer.
   SI = 0;

   while(1){
   for(i=0;i<40;i++){
   		sleep_ms(200);
   }
	temp = SLA_READ(0x70);
	sleep_ms(200);
	SLA_SEND(0x72,temp);
	sleep_ms(200);
	sleep_ms(200);
	SLA_SEND(0x74,~temp);
	sleep_ms(200);
	sleep_ms(200);
	sleep_ms(200);
	sleep_ms(200);
   }
   
}

//------------------------------------------------------------------------------------
// Initialization Routines
//------------------------------------------------------------------------------------

//-----------------------------------------------------------------------------
// SYSCLK_Init
//-----------------------------------------------------------------------------
//
// This routine initializes the system clock to use an 22.1184MHz crystal
// as its clock source.
//
void SYSCLK_Init (void)
{
   int i;                                 // delay counter

   OSCXCN = 0x67;                         // start external oscillator with
                                          // 22.1184MHz crystal

   for (i=0; i < 256; i++) ;              // XTLVLD blanking interval (>1ms)

   while (!(OSCXCN & 0x80)) ;             // Wait for crystal osc. to settle

   OSCICN = 0x88;                         // select external oscillator as SYSCLK
                                          // source and enable missing clock
                                          // detector
}

//------------------------------------------------------------------------------------
// Functions
//------------------------------------------------------------------------------------

// Send to slave.
// The send function transmits two bytes to the slave device: an op code, and a data
// byte.  There are two op code choices for sending data: WRITE_DAC and WRITE_BUF.
// If the op code is WRITE_BUF, then the upper 4 bits of the op code should contain
// the buffer index.  For example, to write to index 2 of the data buffer, the
// op_code parameter should be (0x20 | WRITE_BUF).
//
// chip_select = address of slave device.
// out_op = OP_CODE to be sent.
// out_data = data byte to be sent.
void SLA_SEND(char chip_select, char wr_data)
{
   SENDMODE=0x01;
   while(SM_BUSY);                        // Wait while SMBus is busy.
   SM_BUSY = 1;                           // SMBus busy flag set.
   SMB0CN = 0x44;                         // SMBus enabled, ACK low.
   COMMAND = (chip_select | WRITE);       // COMMAND = 7 address bits + WRITE.
   WORD = wr_data;                       // DATA = data to be transmitted.
   STO = 0;
   STA = 1;                               // Start transfer.
	while(SM_BUSY);   
}

// Read from slave.
// The read function transmits a 1-byte op code, then issues a repeated start
// to request a 1-byte read.  The two op code choices are READ_ADC and READ_BUF.
// If the op code is READ_BUF, then the upper 4 bits of the op code should
// contain the buffer index.  For example, to read index 5 of the data buffer,
// the op code should be (0x50 | READ_BUF).
//
// chip_select = address of slave device.
// out_op = OP_CODE to be sent.
char SLA_READ(char chip_select){
   SENDMODE=0;
   while(SM_BUSY);                        // Wait while SMBus is busy.
   SM_BUSY = 1;                           // Set busy flag.
   SMB0CN = 0x44;                         // Enable SMBus, ACK low.
   COMMAND = (chip_select | READ);        // COMMAND = 7 address bits + READ
   //COMMAND = (chip_select | WRITE); 
   STO = 0;
   STA = 1;                               // Start transfer.
   while(SM_BUSY);                        // Wait for transfer to finish.
   return WORD;                           // Return received word.

}





//------------------------------------------------------------------------------------
// SMBus Interrupt Service Routine
//------------------------------------------------------------------------------------

void SMBUS_ISR (void) interrupt 7
{
   switch (SMB0STA){                    // Status code for the SMBus 
                                        // (SMB0STA register)

      // Master Transmitter/Receiver: START condition transmitted.
      // Load SMB0DAT with slave device address.  Mask out R/W bit since all transfers
      // start with an OP_CODE write.
      case SMB_START:	//0x08
         SMB0DAT = COMMAND ;			// Load address of the slave to be accessed.
                                        // Mask out R/W bit because first transfer
                                        // will always be a write of the OP_CODE.
         STA = 0;                       // Manually clear STA bit
         SI = 0;                        // Clear interrupt flag
         break;

      // Master Transmitter/Receiver: Repeated START condition transmitted.
      // This state only occurs during a READ, after the OP_CODE has been sent.  Load
      // device address + READ into SMB0DAT.
      case SMB_RP_START:	//0x10
         SMB0DAT = COMMAND1;
         STA = 0;                       // Manually clear START bit.
         SI = 0;
         break;

      // Master Transmitter: Slave address + WRITE transmitted.  ACK received.
      // Load OP_CODE into SMB0DAT.
      case SMB_MTADDACK:	//0x18
         _nop_();
		 SMB0DAT = WORD;
         SI = 0;                        // Clear interrupt flag
         break;

      // Master Transmitter: Data byte transmitted.  ACK received.
      // Check OP_CODE - If it is a READ code, send repeated START to begin
      // read.  If it is a WRITE code, load WORD into SMB0DAT for transfer.
      // If it is not a valid code, then either 1) data has been transmitted
      // and the transfer is finished, or 2) there is an error.  In either case,
      // send STOP and end transfer.
      case SMB_MTDBACK:		//0x28
			STO = 1;
			SM_BUSY=0;
         SI = 0;
         break;

      // Master Receiver: Slave address + READ transmitted.  ACK received.
      // Set to transmit NACK after next transfer since it will be the 
      // last (only) byte.
      case SMB_MRADDACK:	//0x40
         AA = 0;                          // NACK sent during acknowledge cycle.
         SI = 0;
         break;

      // Master Receiver: Data byte received.  NACK transmitted.
      // Read operation has completed.  Read data register and send STOP.
      case SMB_MRDBNACK:	//0x58
         WORD = SMB0DAT;
         STO = 1;
         SM_BUSY = 0;
         AA = 1;                          // Set AA for next transfer
         SI = 0;
         break;

      // All other status codes invalid.  Reset communication.
      default:
         STO = 1;
         SM_BUSY = 0;
         break;
      }

}