lm74.c

这是一个有关C8051F020单片机的实验教学材料,相信对于单片机的研究人员会有很大的帮助.

#include <c8051f020.h>                 // SFR declarations
#include <intrins.h>

sbit  CS = P1^0;

#define	SYSCLK			11059200
#define CHIP_SELECT		CS=0, _nop_(), _nop_(), _nop_(), _nop_(), _nop_(), _nop_(), _nop_(), _nop_(), _nop_();
#define CHIP_NOSELECT	CS=1, _nop_(), _nop_(), _nop_(), _nop_(), _nop_(), _nop_(),_nop_(), _nop_(), _nop_();

#define  WRITE       0x00                 // WRITE direction bit
#define  READ        0x01                 // READ direction bit

#define  CHIP_B      0x70
#define  SMB_START      0x08              // (MT & MR) START transmitted
#define  SMB_MTADDACK   0x18              // (MT) Slave address + W transmitted;
                                          //  ACK received
#define  SMB_MTDBACK    0x28              // (MT) data byte transmitted; ACK rec'vd
#define  SMB_MRDBNACK   0x58              // (MR) data byte rec'vd; NACK transmitted

//-----------------------------------------------------------------------------------
//Global VARIABLES
//-----------------------------------------------------------------------------------

char COMMAND;                             // Holds the slave address + R/W bit for
unsigned char totalnumber,sendnumber;                               // OR data that has just been received.
unsigned char xdata SENDMODE;                                         // that has just been received.

bit SM_BUSY;                              // This bit is set when a send or receive
                                          // is started. It is cleared by the
                                     
unsigned char wr_data[8];
unsigned char rd_data[8];

void sleep_ms(unsigned int count)
{
	unsigned char ii,jj;
	for(ii=0;ii<count;ii++)
	{
		for(jj=0;jj<250;jj++)
		_nop_();
	}
}

void SPIWrOne(unsigned char ch)
{
	SPIF = 0;
	SPI0DAT = ch;
	while (SPIF == 0);	 			// wait for data transfer to be completed
	
} 

void SYSCLK_Init (void)
{
	//OSCICN = 0x16;
	int i;                              // delay counter
	OSCXCN = 0x67;                      // start external oscillator with
	                                    // 11.0592MHz crystal
	for (i=0; i < 256; i++) ;           // Wait for osc. to start up
	while (!(OSCXCN & 0x80)) ;          // Wait for crystal osc. to settle
	OSCICN = 0x88;                      // select external oscillator as SYSCLK
	                                    // source and enable missing clock
}

void PORT_Init (void)
{
	XBR0    = 0x07;                     // Enable SMBus, SPI0, and UART0
	XBR1    = 0x00;
	XBR2    = 0x40;                     // Enable crossbar and weak pull-ups
}

void SPI0_Init (void)
{
	SPI0CFG = 0x07;                     // data sampled on 1st SCK rising edge
                                       	// 8-bit data words
	SPI0CFG|=0xC0;						//CKPOL =1;

	SPI0CN = 0x03;                      // Master mode; SPI enabled; flags
                                       	// cleared
	SPI0CKR = 39;
	 
}

void SLA_SEND(char chip_select, char *wr_data, char number)
{
   SENDMODE=0x01;
   totalnumber=number;
   sendnumber=number;
   while(SM_BUSY);                        // Wait while SMBus is busy.
   SM_BUSY = 1;                           // SMBus busy flag set.
   SMB0CN = 0x44;                         // SMBus enabled, ACK low.
   COMMAND = (chip_select | WRITE);       // COMMAND = 7 address bits + WRITE.
   STO = 0;
   STA = 1;                               // Start transfer.
	while(SM_BUSY);   
}

void main (void) 
{
	unsigned char temp;
	unsigned char TempH,TempL;
	unsigned int w;
	unsigned char Number[16]={0x3f,0x06,0x5b,0x4f,0x66,0x6d,0x7d,0x07,0x7f,0x6f,0x77,0x7c,0x39,0x5e,0x79,0x71};
	WDTCN = 0xde;                       // disable watchdog timer
	WDTCN = 0xad;
	SYSCLK_Init ();                     // initialize oscillator
	PORT_Init ();                       // initialize crossbar and GPIO
	SPI0_Init ();                       // initialize SPI0
	SMB0CN = 0x44;                         // Enable SMBus with acknowledge low (AA = 1)
	SMB0CR = -80;                          // SMBus clock rate = 100 kHz
	EIE1 |= 2;                             // SMBus interrupt enable
	SM_BUSY = 0;                           // Free bus for first transfer.
	SI = 0;
	EA=1;					//开中断
	while(1)
	{
		sleep_ms(250);
		sleep_ms(250);
		sleep_ms(250);
		CHIP_SELECT;
		SPIWrOne(0x01);
		TempH=SPI0DAT;
		SPIWrOne(0x01);
		TempL=SPI0DAT;
		CHIP_NOSELECT;
		w = TempH*0x100+TempL;
		w = w>>3;
		w =w *0.625;

		wr_data[0] = 0x00;
		wr_data[1] = 0x17;
		wr_data[2] = 0x00;
		temp = (w%1000)/100;
		wr_data[3] = Number[temp];
		temp = (w%100)/10;
		wr_data[4] = Number[temp]|0x80;
		temp = (w%10);
		wr_data[5] = Number[temp];
		SLA_SEND(CHIP_B,wr_data,0x06);
		sleep_ms(250);
		sleep_ms(250);
		sleep_ms(250);
		sleep_ms(250);
		_nop_();
	}
}

//------------------------------------------------------------------------------------
// SMBus Interrupt Service Routine
//------------------------------------------------------------------------------------

void SMBUS_ISR (void) interrupt 7
{
   switch (SMB0STA){                    // Status code for the SMBus 
                                        // (SMB0STA register)

      // Master Transmitter/Receiver: START condition transmitted.
      // Load SMB0DAT with slave device address.  Mask out R/W bit since all transfers
      // start with an OP_CODE write.
      case SMB_START:	//0x08
         SMB0DAT = COMMAND ;			// Load address of the slave to be accessed.
                                        // Mask out R/W bit because first transfer
                                        // will always be a write of the OP_CODE.
         STA = 0;                       // Manually clear STA bit
         SI = 0;                        // Clear interrupt flag
         break;

      // Master Transmitter: Slave address + WRITE transmitted.  ACK received.
      // Load OP_CODE into SMB0DAT.
      case SMB_MTADDACK:	//0x18
         SMB0DAT = wr_data[0];
         SI = 0;                        // Clear interrupt flag
         break;

      // Master Transmitter: Data byte transmitted.  ACK received.
      // Check OP_CODE - If it is a READ code, send repeated START to begin
      // read.  If it is a WRITE code, load WORD into SMB0DAT for transfer.
      // If it is not a valid code, then either 1) data has been transmitted
      // and the transfer is finished, or 2) there is an error.  In either case,
      // send STOP and end transfer.
      case SMB_MTDBACK:		//0x28
         switch (SENDMODE){         	// Check only lower 4 bits.

            // OP_CODE is a READ.  Send repeated START.
            case 1:
			   sendnumber--;
			   if(sendnumber)
			   SMB0DAT = wr_data[totalnumber-sendnumber];
			   else{
			   		STO=1;
				   	SM_BUSY=0;
				}

               //OP_CODE = 0;               // Clear OP_CODE so transfer ends the next
               break;                     // time this state occurs 
            case 0:
			     STO = 0;
               STA = 1;
               break;                          // (after data is sent).

		
            default:                      // No valid OP_CODE.  End transfer.
               STO = 1;
               SM_BUSY = 0;
               break;
         }
         SI = 0;
         break;


      // Master Receiver: Data byte received.  NACK transmitted.
      // Read operation has completed.  Read data register and send STOP.
      case SMB_MRDBNACK:	//0x58
         rd_data[0] = SMB0DAT;
         STO = 1;
         SM_BUSY = 0;
         AA = 1;                          // Set AA for next transfer
         SI = 0;
         break;

		// All other status codes invalid.  Reset communication.
      default:
         STO = 1;
         SM_BUSY = 0;
         break;
      }

}