fw-decoder-regs.txt

linux 内核源代码

2900
      bits 0:31
	Decoder vertical Y alias register 1
---------------
2904
      bits 0:31
	Decoder vertical Y alias register 2
---------------
2908
      bits 0:31
	Decoder vertical Y alias trigger

     These three registers control the vertical aliasing filter for the Y plane.
     Operation is similar to the horizontal Y filter (2804). The only real
     difference is that there are only two registers to set before accessing
     the trigger register (2908). As for the horizontal filter, the values are
     taken from a lookup table in the firmware, and the procedure must be
     repeated 16 times to fully program the filter.
--------------------------------------------------------------------------------
290C
      bits 0:31
	Decoder vertical UV alias register 1
---------------
2910
      bits 0:31
	Decoder vertical UV alias register 2
---------------
2914
      bits 0:31
	Decoder vertical UV alias trigger

     These three registers control the vertical aliasing filter for the UV
     plane. Operation is the same as the Y filter, with 2914 being the trigger.
--------------------------------------------------------------------------------
2918
      bits 0:15
	Decoder Y source height in pixels

      bits 16:31
	Decoder Y destination height in pixels
---------------
291C
      bits 0:15
	Decoder UV source height in pixels divided by 2

      bits 16:31
	Decoder UV destination height in pixels

     NOTE: For both registers, the resulting image must be fully visible on
     screen. If the image exceeds the bottom edge both the source and
     destination size must be adjusted to reflect the visible portion. For the
     source height, you must take into account the scaling when calculating the
     new value.
--------------------------------------------------------------------------------
2920
      bits 0:31
	Decoder Y vertical scaling
	  Normally = Reg 2930 >> 2
---------------
2924
      bits 0:31
	Decoder Y vertical scaling
	  Normally = Reg 2920 + 0x514
---------------
2928
      bits 0:31
	Decoder UV vertical scaling
	  When enlarging = Reg 2930 >> 2
	  When reducing = Reg 2930 >> 3
---------------
292C
      bits 0:31
	Decoder UV vertical scaling
	  Normally = Reg 2928 + 0x514
---------------
2930
      bits 0:31
	Decoder 'master' value for vertical scaling
---------------
2934
      bits 0:31
	Decoder ?? unknown - Y vertical scaling
---------------
2938
      bits 0:31
	Decoder Y vertical scaling
	  Normally = Reg 2930
---------------
293C
      bits 0:31
	Decoder ?? unknown - Y vertical scaling
---------------
2940
      bits 0:31
	Decoder UV vertical scaling
	  When enlarging = Reg 2930 >> 1
	  When reducing = Reg 2930
---------------
2944
      bits 0:31
	Decoder ?? unknown - UV vertical scaling
---------------
2948
      bits 0:31
	Decoder UV vertical scaling
	  Normally = Reg 2940
---------------
294C
      bits 0:31
	Decoder ?? unknown - UV vertical scaling

     Most of these registers either control vertical scaling, or appear linked
     to it in some way. Register 2930 contains the 'master' value & all other
     registers can be calculated from that one. You must also remember to
     correctly set the divider in Reg 296C

     To enlarge:
	     Reg 2930 = (source_height * 0x00200000) / destination_height
	     Reg 296C = No divide

     To reduce from full size down to half size:
	     Reg 2930 = (source_height/2 * 0x00200000) / destination height
	     Reg 296C = Divide by 2

      To reduce from half down to quarter.
	     Reg 2930 = (source_height/4 * 0x00200000) / destination height
	     Reg 296C = Divide by 4

--------------------------------------------------------------------------------
2950
      bits 0:15
	Decoder Y line index into display buffer, first field

      bits 16:31
	Decoder Y vertical line skip, first field
--------------------------------------------------------------------------------
2954
      bits 0:15
	Decoder Y line index into display buffer, second field

      bits 16:31
	Decoder Y vertical line skip, second field
--------------------------------------------------------------------------------
2958
      bits 0:15
	Decoder UV line index into display buffer, first field

      bits 16:31
	Decoder UV vertical line skip, first field
--------------------------------------------------------------------------------
295C
      bits 0:15
	Decoder UV line index into display buffer, second field

      bits 16:31
	Decoder UV vertical line skip, second field
--------------------------------------------------------------------------------
2960
      bits 0:15
	Decoder destination height minus 1

      bits 16:31
	Decoder destination height divided by 2
--------------------------------------------------------------------------------
2964
      bits 0:15
	Decoder Y vertical offset, second field

      bits 16:31
	Decoder Y vertical offset, first field

     These two registers shift the Y plane up. The higher the number, the
     greater the shift.
--------------------------------------------------------------------------------
2968
      bits 0:15
	Decoder UV vertical offset, second field

      bits 16:31
	Decoder UV vertical offset, first field

     These two registers shift the UV plane up. The higher the number, the
     greater the shift.
--------------------------------------------------------------------------------
296C
      bits 0:1
	Decoder vertical Y output size divider
	  00 = No divide
	  01 = Divide by 2
	  10 = Divide by 4

      bits 8:9
	Decoder vertical UV output size divider
	  00 = No divide
	  01 = Divide by 2
	  10 = Divide by 4
--------------------------------------------------------------------------------
2970
      bit 0
	Decoder ?? unknown
	  0 = Normal
	  1 = Affect video output levels

      bit 16
	Decoder ?? unknown
	  0 = Normal
	  1 = Disable vertical filter

--------------------------------------------------------------------------------
2974  --------   ?? unknown
 |
 V
29EF  --------   ?? unknown
--------------------------------------------------------------------------------
2A00
      bits 0:2
	osd colour mode
	  000 = 8 bit indexed
	  001 = 16 bit (565)
	  010 = 15 bit (555)
	  011 = 12 bit (444)
	  100 = 32 bit (8888)

      bits 4:5
	osd display bpp
	  01 = 8 bit
	  10 = 16 bit
	  11 = 32 bit

      bit 8
	osd global alpha
	  0 = Off
	  1 = On

      bit 9
	osd local alpha
	  0 = Off
	  1 = On

      bit 10
	osd colour key
	  0 = Off
	  1 = On

      bit 11
	osd ?? unknown
	  Must be 1

      bit 13
	osd colour space
	  0 = ARGB
	  1 = AYVU

      bits 16:31
	osd ?? unknown
	  Must be 0x001B (some kind of buffer pointer ?)

     When the bits-per-pixel is set to 8, the colour mode is ignored and
     assumed to be 8 bit indexed. For 16 & 32 bits-per-pixel the colour depth
     is honoured, and when using a colour depth that requires fewer bytes than
     allocated the extra bytes are used as padding. So for a 32 bpp with 8 bit
     index colour, there are 3 padding bytes per pixel. It's also possible to
     select 16bpp with a 32 bit colour mode. This results in the pixel width
     being doubled, but the color key will not work as expected in this mode.

     Colour key is as it suggests. You designate a colour which will become
     completely transparent. When using 565, 555 or 444 colour modes, the
     colour key is always 16 bits wide. The colour to key on is set in Reg 2A18.

     Local alpha works differently depending on the colour mode. For 32bpp & 8
     bit indexed, local alpha is a per-pixel 256 step transparency, with 0 being
     transparent and 255 being solid. For the 16bpp modes 555 & 444, the unused
     bit(s) act as a simple transparency switch, with 0 being solid & 1 being
     fully transparent. There is no local alpha support for 16bit 565.

     Global alpha is a 256 step transparency that applies to the entire osd,
     with 0 being transparent & 255 being solid.

     It's possible to combine colour key, local alpha & global alpha.
--------------------------------------------------------------------------------
2A04
      bits 0:15
	osd x coord for left edge

      bits 16:31
	osd y coord for top edge
---------------
2A08
      bits 0:15
	osd x coord for right edge

      bits 16:31
	osd y coord for bottom edge

     For both registers, (0,0) = top left corner of the display area. These
     registers do not control the osd size, only where it's positioned & how
     much is visible. The visible osd area cannot exceed the right edge of the
     display, otherwise the osd will become corrupt. See reg 2A10 for
     setting osd width.
--------------------------------------------------------------------------------
2A0C
      bits 0:31
	osd buffer index

     An index into the osd buffer. Slowly incrementing this moves the osd left,
     wrapping around onto the right edge
--------------------------------------------------------------------------------
2A10
      bits 0:11
	osd buffer 32 bit word width

     Contains the width of the osd measured in 32 bit words. This means that all
     colour modes are restricted to a byte width which is divisible by 4.
--------------------------------------------------------------------------------
2A14
      bits 0:15
	osd height in pixels

      bits 16:32
	osd line index into buffer
	  osd will start displaying from this line.
--------------------------------------------------------------------------------
2A18
      bits 0:31
	osd colour key

     Contains the colour value which will be transparent.
--------------------------------------------------------------------------------
2A1C
      bits 0:7
	osd global alpha

     Contains the global alpha value (equiv ivtvfbctl --alpha XX)
--------------------------------------------------------------------------------
2A20  --------    ?? unknown
 |
 V
2A2C  --------    ?? unknown
--------------------------------------------------------------------------------
2A30
      bits 0:7
	osd colour to change in indexed palette
---------------
2A34
      bits 0:31
	osd colour for indexed palette

     To set the new palette, first load the index of the colour to change into
     2A30, then load the new colour into 2A34. The full palette is 256 colours,
     so the index range is 0x00-0xFF
--------------------------------------------------------------------------------
2A38  --------    ?? unknown
2A3C  --------    ?? unknown
--------------------------------------------------------------------------------
2A40
      bits 0:31
	osd ?? unknown

     Affects overall brightness, wrapping around to black
--------------------------------------------------------------------------------
2A44
      bits 0:31
	osd ?? unknown

     Green tint
--------------------------------------------------------------------------------
2A48
      bits 0:31
	osd ?? unknown

     Red tint
--------------------------------------------------------------------------------
2A4C
      bits 0:31
	osd ?? unknown

     Affects overall brightness, wrapping around to black
--------------------------------------------------------------------------------
2A50
      bits 0:31
	osd ?? unknown

     Colour shift
--------------------------------------------------------------------------------
2A54
      bits 0:31
	osd ?? unknown

     Colour shift
--------------------------------------------------------------------------------
2A58  --------    ?? unknown
 |
 V
2AFC  --------    ?? unknown
--------------------------------------------------------------------------------
2B00
      bit 0
	osd filter control
	  0 = filter off
	  1 = filter on

      bits 1:4
	osd ?? unknown

--------------------------------------------------------------------------------

v0.4 - 12 March 2007 - Ian Armstrong ([e-mail])