📄 fw-decoder-regs.txt
字号:
PVR350 Video decoder registers 0x02002800 -> 0x02002B00=======================================================This list has been worked out through trial and error. There will be mistakesand omissions. Some registers have no obvious effect so it's hard to say whatthey do, while others interact with each other, or require a certain loadsequence. Horizontal filter setup is one example, with six registers workingin unison and requiring a certain load sequence to correctly configure. Theindexed colour palette is much easier to set at just two registers, but againit requires a certain load sequence.Some registers are fussy about what they are set to. Load in a bad value & thedecoder will fail. A firmware reload will often recover, but sometimes a resetis required. For registers containing size information, setting them to 0 isgenerally a bad idea. For other control registers i.e. 2878, you'll only findout what values are bad when it hangs.--------------------------------------------------------------------------------2800 bit 0 Decoder enable 0 = disable 1 = enable--------------------------------------------------------------------------------2804 bits 0:31 Decoder horizontal Y alias register 1---------------2808 bits 0:31 Decoder horizontal Y alias register 2---------------280C bits 0:31 Decoder horizontal Y alias register 3---------------2810 bits 0:31 Decoder horizontal Y alias register 4---------------2814 bits 0:31 Decoder horizontal Y alias register 5---------------2818 bits 0:31 Decoder horizontal Y alias trigger These six registers control the horizontal aliasing filter for the Y plane. The first five registers must all be loaded before accessing the trigger (2818), as this register actually clocks the data through for the first five. To correctly program set the filter, this whole procedure must be done 16 times. The actual register contents are copied from a lookup-table in the firmware which contains 4 different filter settings.--------------------------------------------------------------------------------281C bits 0:31 Decoder horizontal UV alias register 1---------------2820 bits 0:31 Decoder horizontal UV alias register 2---------------2824 bits 0:31 Decoder horizontal UV alias register 3---------------2828 bits 0:31 Decoder horizontal UV alias register 4---------------282C bits 0:31 Decoder horizontal UV alias register 5---------------2830 bits 0:31 Decoder horizontal UV alias trigger These six registers control the horizontal aliasing for the UV plane. Operation is the same as the Y filter, with 2830 being the trigger register.--------------------------------------------------------------------------------2834 bits 0:15 Decoder Y source width in pixels bits 16:31 Decoder Y destination width in pixels---------------2838 bits 0:15 Decoder UV source width in pixels bits 16:31 Decoder UV destination width in pixels NOTE: For both registers, the resulting image must be fully visible on screen. If the image exceeds the right edge both the source and destination size must be adjusted to reflect the visible portion. For the source width, you must take into account the scaling when calculating the new value.--------------------------------------------------------------------------------283C bits 0:31 Decoder Y horizontal scaling Normally = Reg 2854 >> 2---------------2840 bits 0:31 Decoder ?? unknown - horizontal scaling Usually 0x00080514---------------2844 bits 0:31 Decoder UV horizontal scaling Normally = Reg 2854 >> 2---------------2848 bits 0:31 Decoder ?? unknown - horizontal scaling Usually 0x00100514---------------284C bits 0:31 Decoder ?? unknown - Y plane Usually 0x00200020---------------2850 bits 0:31 Decoder ?? unknown - UV plane Usually 0x00200020---------------2854 bits 0:31 Decoder 'master' value for horizontal scaling---------------2858 bits 0:31 Decoder ?? unknown Usually 0---------------285C bits 0:31 Decoder ?? unknown Normally = Reg 2854 >> 1---------------2860 bits 0:31 Decoder ?? unknown Usually 0---------------2864 bits 0:31 Decoder ?? unknown Normally = Reg 2854 >> 1---------------2868 bits 0:31 Decoder ?? unknown Usually 0 Most of these registers either control horizontal scaling, or appear linked to it in some way. Register 2854 contains the 'master' value & the other registers can be calculated from that one. You must also remember to correctly set the divider in Reg 2874. To enlarge: Reg 2854 = (source_width * 0x00200000) / destination_width Reg 2874 = No divide To reduce from full size down to half size: Reg 2854 = (source_width/2 * 0x00200000) / destination width Reg 2874 = Divide by 2 To reduce from half size down to quarter size: Reg 2854 = (source_width/4 * 0x00200000) / destination width Reg 2874 = Divide by 4 The result is always rounded up.--------------------------------------------------------------------------------286C bits 0:15 Decoder horizontal Y buffer offset bits 15:31 Decoder horizontal UV buffer offset Offset into the video image buffer. If the offset is gradually incremented, the on screen image will move left & wrap around higher up on the right.--------------------------------------------------------------------------------2870 bits 0:15 Decoder horizontal Y output offset bits 16:31 Decoder horizontal UV output offset Offsets the actual video output. Controls output alignment of the Y & UV planes. The higher the value, the greater the shift to the left. Use reg 2890 to move the image right.--------------------------------------------------------------------------------2874 bits 0:1 Decoder horizontal Y output size divider 00 = No divide 01 = Divide by 2 10 = Divide by 3 bits 4:5 Decoder horizontal UV output size divider 00 = No divide 01 = Divide by 2 10 = Divide by 3 bit 8 Decoder ?? unknown 0 = Normal 1 = Affects video output levels bit 16 Decoder ?? unknown 0 = Normal 1 = Disable horizontal filter--------------------------------------------------------------------------------2878 bit 0 ?? unknown bit 1 osd on/off 0 = osd off 1 = osd on bit 2 Decoder + osd video timing 0 = NTSC 1 = PAL bits 3:4 ?? unknown bit 5 Decoder + osd Swaps upper & lower fields--------------------------------------------------------------------------------287C bits 0:10 Decoder & osd ?? unknown Moves entire screen horizontally. Starts at 0x005 with the screen shifted heavily to the right. Incrementing in steps of 0x004 will gradually shift the screen to the left. bits 11:31 ?? unknown Normally contents are 0x00101111 (NTSC) or 0x1010111d (PAL)--------------------------------------------------------------------------------2880 -------- ?? unknown2884 -------- ?? unknown--------------------------------------------------------------------------------2888 bit 0 Decoder + osd ?? unknown 0 = Normal 1 = Misaligned fields (Correctable through 289C & 28A4) bit 4 ?? unknown bit 8 ?? unknown Warning: Bad values will require a firmware reload to recover. Known to be bad are 0x000,0x011,0x100,0x111--------------------------------------------------------------------------------288C bits 0:15 osd ?? unknown Appears to affect the osd position stability. The higher the value the more unstable it becomes. Decoder output remains stable. bits 16:31 osd ?? unknown Same as bits 0:15--------------------------------------------------------------------------------2890 bits 0:11 Decoder output horizontal offset. Horizontal offset moves the video image right. A small left shift is possible, but it's better to use reg 2870 for that due to its greater range. NOTE: Video corruption will occur if video window is shifted off the right edge. To avoid this read the notes for 2834 & 2838.--------------------------------------------------------------------------------2894 bits 0:23 Decoder output video surround colour. Contains the colour (in yuv) used to fill the screen when the video is running in a window.--------------------------------------------------------------------------------2898 bits 0:23 Decoder video window colour Contains the colour (in yuv) used to fill the video window when the video is turned off. bit 24 Decoder video output 0 = Video on 1 = Video off bit 28 Decoder plane order 0 = Y,UV 1 = UV,Y bit 29 Decoder second plane byte order 0 = Normal (UV) 1 = Swapped (VU) In normal usage, the first plane is Y & the second plane is UV. Though the order of the planes can be swapped, only the byte order of the second plane can be swapped. This isn't much use for the Y plane, but can be useful for the UV plane.--------------------------------------------------------------------------------289C bits 0:15 Decoder vertical field offset 1 bits 16:31 Decoder vertical field offset 2 Controls field output vertical alignment. The higher the number, the lower the image on screen. Known starting values are 0x011E0017 (NTSC) & 0x01500017 (PAL)--------------------------------------------------------------------------------28A0 bits 0:15 Decoder & osd width in pixels bits 16:31 Decoder & osd height in pixels All output from the decoder & osd are disabled beyond this area. Decoder output will simply go black outside of this region. If the osd tries to exceed this area it will become corrupt.--------------------------------------------------------------------------------28A4 bits 0:11 osd left shift. Has a range of 0x770->0x7FF. With the exception of 0, any value outside of this range corrupts the osd.--------------------------------------------------------------------------------28A8 bits 0:15 osd vertical field offset 1 bits 16:31 osd vertical field offset 2 Controls field output vertical alignment. The higher the number, the lower the image on screen. Known starting values are 0x011E0017 (NTSC) & 0x01500017 (PAL)--------------------------------------------------------------------------------28AC -------- ?? unknown | V28BC -------- ?? unknown--------------------------------------------------------------------------------28C0 bit 0 Current output field 0 = first field 1 = second field bits 16:31 Current scanline The scanline counts from the top line of the first field through to the last line of the second field.--------------------------------------------------------------------------------28C4 -------- ?? unknown | V28F8 -------- ?? unknown--------------------------------------------------------------------------------28FC bit 0 ?? unknown 0 = Normal 1 = Breaks decoder & osd output--------------------------------------------------------------------------------⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -