echoaudio_dsp.h

linux 内核源代码

/****************************************************************************

   Copyright Echo Digital Audio Corporation (c) 1998 - 2004
   All rights reserved
   www.echoaudio.com

   This file is part of Echo Digital Audio's generic driver library.

   Echo Digital Audio's generic driver library is free software;
   you can redistribute it and/or modify it under the terms of
   the GNU General Public License as published by the Free Software
   Foundation.

   This program is distributed in the hope that it will be useful,
   but WITHOUT ANY WARRANTY; without even the implied warranty of
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
   GNU General Public License for more details.

   You should have received a copy of the GNU General Public License
   along with this program; if not, write to the Free Software
   Foundation, Inc., 59 Temple Place - Suite 330, Boston,
   MA  02111-1307, USA.

   *************************************************************************

 Translation from C++ and adaptation for use in ALSA-Driver
 were made by Giuliano Pochini <[e-mail]>

****************************************************************************/

#ifndef _ECHO_DSP_
#define _ECHO_DSP_


/**** Echogals: Darla20, Gina20, Layla20, and Darla24 ****/
#if defined(ECHOGALS_FAMILY)

#define NUM_ASIC_TESTS		5
#define READ_DSP_TIMEOUT	1000000L	/* one second */

/**** Echo24: Gina24, Layla24, Mona, Mia, Mia-midi ****/
#elif defined(ECHO24_FAMILY)

#define DSP_56361			/* Some Echo24 cards use the 56361 DSP */
#define READ_DSP_TIMEOUT	100000L		/* .1 second */

/**** 3G: Gina3G, Layla3G ****/
#elif defined(ECHO3G_FAMILY)

#define DSP_56361
#define READ_DSP_TIMEOUT 	100000L		/* .1 second */
#define MIN_MTC_1X_RATE		32000

/**** Indigo: Indigo, Indigo IO, Indigo DJ ****/
#elif defined(INDIGO_FAMILY)

#define DSP_56361
#define READ_DSP_TIMEOUT	100000L		/* .1 second */

#else

#error No family is defined

#endif



/*
 *
 *  Max inputs and outputs
 *
 */

#define DSP_MAXAUDIOINPUTS		16	/* Max audio input channels */
#define DSP_MAXAUDIOOUTPUTS		16	/* Max audio output channels */
#define DSP_MAXPIPES			32	/* Max total pipes (input + output) */


/*
 *
 * These are the offsets for the memory-mapped DSP registers; the DSP base
 * address is treated as the start of a u32 array.
 */

#define CHI32_CONTROL_REG		4
#define CHI32_STATUS_REG		5
#define CHI32_VECTOR_REG		6
#define CHI32_DATA_REG			7


/*
 *
 * Interesting bits within the DSP registers
 *
 */

#define CHI32_VECTOR_BUSY		0x00000001
#define CHI32_STATUS_REG_HF3		0x00000008
#define CHI32_STATUS_REG_HF4		0x00000010
#define CHI32_STATUS_REG_HF5		0x00000020
#define CHI32_STATUS_HOST_READ_FULL	0x00000004
#define CHI32_STATUS_HOST_WRITE_EMPTY	0x00000002
#define CHI32_STATUS_IRQ		0x00000040


/* 
 *
 * DSP commands sent via slave mode; these are sent to the DSP by write_dsp()
 *
 */

#define DSP_FNC_SET_COMMPAGE_ADDR		0x02
#define DSP_FNC_LOAD_LAYLA_ASIC			0xa0
#define DSP_FNC_LOAD_GINA24_ASIC		0xa0
#define DSP_FNC_LOAD_MONA_PCI_CARD_ASIC		0xa0
#define DSP_FNC_LOAD_LAYLA24_PCI_CARD_ASIC	0xa0
#define DSP_FNC_LOAD_MONA_EXTERNAL_ASIC		0xa1
#define DSP_FNC_LOAD_LAYLA24_EXTERNAL_ASIC	0xa1
#define DSP_FNC_LOAD_3G_ASIC			0xa0


/*
 *
 * Defines to handle the MIDI input state engine; these are used to properly
 * extract MIDI time code bytes and their timestamps from the MIDI input stream.
 *
 */

#define MIDI_IN_STATE_NORMAL	0
#define MIDI_IN_STATE_TS_HIGH	1
#define MIDI_IN_STATE_TS_LOW	2
#define MIDI_IN_STATE_F1_DATA 	3
#define MIDI_IN_SKIP_DATA	(-1)


/*----------------------------------------------------------------------------

Setting the sample rates on Layla24 is somewhat schizophrenic.

For standard rates, it works exactly like Mona and Gina24.  That is, for
8, 11.025, 16, 22.05, 32, 44.1, 48, 88.2, and 96 kHz, you just set the
appropriate bits in the control register and write the control register.

In order to support MIDI time code sync (and possibly SMPTE LTC sync in
the future), Layla24 also has "continuous sample rate mode".  In this mode,
Layla24 can generate any sample rate between 25 and 50 kHz inclusive, or
50 to 100 kHz inclusive for double speed mode.

To use continuous mode:

-Set the clock select bits in the control register to 0xe (see the #define
 below)

-Set double-speed mode if you want to use sample rates above 50 kHz

-Write the control register as you would normally

-Now, you need to set the frequency register. First, you need to determine the
 value for the frequency register.  This is given by the following formula:

frequency_reg = (LAYLA24_MAGIC_NUMBER / sample_rate) - 2

Note the #define below for the magic number

-Wait for the DSP handshake
-Write the frequency_reg value to the .SampleRate field of the comm page
-Send the vector command SET_LAYLA24_FREQUENCY_REG (see vmonkey.h)

Once you have set the control register up for continuous mode, you can just
write the frequency register to change the sample rate.  This could be
used for MIDI time code sync. For MTC sync, the control register is set for
continuous mode.  The driver then just keeps writing the
SET_LAYLA24_FREQUENCY_REG command.

-----------------------------------------------------------------------------*/

#define LAYLA24_MAGIC_NUMBER			677376000
#define LAYLA24_CONTINUOUS_CLOCK		0x000e


/*
 *
 * DSP vector commands
 *
 */

#define DSP_VC_RESET				0x80ff

#ifndef DSP_56361

#define DSP_VC_ACK_INT				0x8073
#define DSP_VC_SET_VMIXER_GAIN			0x0000	/* Not used, only for compile */
#define DSP_VC_START_TRANSFER			0x0075	/* Handshke rqd. */
#define DSP_VC_METERS_ON			0x0079
#define DSP_VC_METERS_OFF			0x007b
#define DSP_VC_UPDATE_OUTVOL			0x007d	/* Handshke rqd. */
#define DSP_VC_UPDATE_INGAIN			0x007f	/* Handshke rqd. */
#define DSP_VC_ADD_AUDIO_BUFFER			0x0081	/* Handshke rqd. */
#define DSP_VC_TEST_ASIC			0x00eb
#define DSP_VC_UPDATE_CLOCKS			0x00ef	/* Handshke rqd. */
#define DSP_VC_SET_LAYLA_SAMPLE_RATE		0x00f1	/* Handshke rqd. */
#define DSP_VC_SET_GD_AUDIO_STATE		0x00f1	/* Handshke rqd. */
#define DSP_VC_WRITE_CONTROL_REG		0x00f1	/* Handshke rqd. */
#define DSP_VC_MIDI_WRITE			0x00f5	/* Handshke rqd. */
#define DSP_VC_STOP_TRANSFER			0x00f7	/* Handshke rqd. */
#define DSP_VC_UPDATE_FLAGS			0x00fd	/* Handshke rqd. */
#define DSP_VC_GO_COMATOSE			0x00f9

#else /* !DSP_56361 */

/* Vector commands for families that use either the 56301 or 56361 */
#define DSP_VC_ACK_INT				0x80F5
#define DSP_VC_SET_VMIXER_GAIN			0x00DB	/* Handshke rqd. */
#define DSP_VC_START_TRANSFER			0x00DD	/* Handshke rqd. */
#define DSP_VC_METERS_ON			0x00EF
#define DSP_VC_METERS_OFF			0x00F1
#define DSP_VC_UPDATE_OUTVOL			0x00E3	/* Handshke rqd. */
#define DSP_VC_UPDATE_INGAIN			0x00E5	/* Handshke rqd. */
#define DSP_VC_ADD_AUDIO_BUFFER			0x00E1	/* Handshke rqd. */
#define DSP_VC_TEST_ASIC			0x00ED
#define DSP_VC_UPDATE_CLOCKS			0x00E9	/* Handshke rqd. */
#define DSP_VC_SET_LAYLA24_FREQUENCY_REG	0x00E9	/* Handshke rqd. */
#define DSP_VC_SET_LAYLA_SAMPLE_RATE		0x00EB	/* Handshke rqd. */
#define DSP_VC_SET_GD_AUDIO_STATE		0x00EB	/* Handshke rqd. */
#define DSP_VC_WRITE_CONTROL_REG		0x00EB	/* Handshke rqd. */
#define DSP_VC_MIDI_WRITE			0x00E7	/* Handshke rqd. */
#define DSP_VC_STOP_TRANSFER			0x00DF	/* Handshke rqd. */
#define DSP_VC_UPDATE_FLAGS			0x00FB	/* Handshke rqd. */
#define DSP_VC_GO_COMATOSE			0x00d9

#endif /* !DSP_56361 */


/*
 *
 * Timeouts
 *
 */

#define HANDSHAKE_TIMEOUT		20000	/* send_vector command timeout (20ms) */
#define VECTOR_BUSY_TIMEOUT		100000	/* 100ms */
#define MIDI_OUT_DELAY_USEC		2000	/* How long to wait after MIDI fills up */


/*
 *
 * Flags for .Flags field in the comm page
 *
 */

#define DSP_FLAG_MIDI_INPUT		0x0001	/* Enable MIDI input */
#define DSP_FLAG_SPDIF_NONAUDIO		0x0002	/* Sets the "non-audio" bit
						 * in the S/PDIF out status
						 * bits.  Clear this flag for
						 * audio data;
						 * set it for AC3 or WMA or
						 * some such */
#define DSP_FLAG_PROFESSIONAL_SPDIF	0x0008	/* 1 Professional, 0 Consumer */


/*
 *
 * Clock detect bits reported by the DSP for Gina20, Layla20, Darla24, and Mia
 *
 */

#define GLDM_CLOCK_DETECT_BIT_WORD	0x0002
#define GLDM_CLOCK_DETECT_BIT_SUPER	0x0004
#define GLDM_CLOCK_DETECT_BIT_SPDIF	0x0008
#define GLDM_CLOCK_DETECT_BIT_ESYNC	0x0010


/*
 *
 * Clock detect bits reported by the DSP for Gina24, Mona, and Layla24
 *
 */

#define GML_CLOCK_DETECT_BIT_WORD96	0x0002
#define GML_CLOCK_DETECT_BIT_WORD48	0x0004
#define GML_CLOCK_DETECT_BIT_SPDIF48	0x0008
#define GML_CLOCK_DETECT_BIT_SPDIF96	0x0010
#define GML_CLOCK_DETECT_BIT_WORD	(GML_CLOCK_DETECT_BIT_WORD96 | GML_CLOCK_DETECT_BIT_WORD48)
#define GML_CLOCK_DETECT_BIT_SPDIF	(GML_CLOCK_DETECT_BIT_SPDIF48 | GML_CLOCK_DETECT_BIT_SPDIF96)
#define GML_CLOCK_DETECT_BIT_ESYNC	0x0020
#define GML_CLOCK_DETECT_BIT_ADAT	0x0040


/*
 *
 * Layla clock numbers to send to DSP
 *
 */

#define LAYLA20_CLOCK_INTERNAL		0
#define LAYLA20_CLOCK_SPDIF		1
#define LAYLA20_CLOCK_WORD		2
#define LAYLA20_CLOCK_SUPER		3


/*
 *
 * Gina/Darla clock states
 *
 */

#define GD_CLOCK_NOCHANGE		0
#define GD_CLOCK_44			1
#define GD_CLOCK_48			2
#define GD_CLOCK_SPDIFIN		3
#define GD_CLOCK_UNDEF			0xff


/*
 *
 * Gina/Darla S/PDIF status bits
 *
 */

#define GD_SPDIF_STATUS_NOCHANGE	0
#define GD_SPDIF_STATUS_44		1
#define GD_SPDIF_STATUS_48		2
#define GD_SPDIF_STATUS_UNDEF		0xff


/*
 *
 * Layla20 output clocks
 *
 */

#define LAYLA20_OUTPUT_CLOCK_SUPER	0
#define LAYLA20_OUTPUT_CLOCK_WORD	1


/****************************************************************************

   Magic constants for the Darla24 hardware

 ****************************************************************************/

#define GD24_96000	0x0
#define GD24_48000	0x1
#define GD24_44100	0x2
#define GD24_32000	0x3
#define GD24_22050	0x4
#define GD24_16000	0x5