ca0106.h

linux 内核源代码

						 * 0x80000000 = Full buffer Playback,Caputre xrun.
						 */
#define EXTENDED_INT            0x76            /* Used by both playback and capture interrupt handler */
						/* Shows which interrupts are active at the moment. */
						/* Same bit layout as EXTENDED_INT_MASK */
#define COUNTER77               0x77		/* Counter range 0 to 0x3fffff, 192000 counts per second. */
#define COUNTER78               0x78		/* Counter range 0 to 0x3fffff, 44100 counts per second. */
#define EXTENDED_INT_TIMER      0x79            /* Channel_id 0 only. Used by both playback and capture interrupt handler */
						/* Causes interrupts based on timer intervals. */
#define SPI			0x7a		/* SPI: Serial Interface Register */
#define I2C_A			0x7b		/* I2C Address. 32 bit */
#define I2C_D0			0x7c		/* I2C Data Port 0. 32 bit */
#define I2C_D1			0x7d		/* I2C Data Port 1. 32 bit */
//I2C values
#define I2C_A_ADC_ADD_MASK	0x000000fe	//The address is a 7 bit address
#define I2C_A_ADC_RW_MASK	0x00000001	//bit mask for R/W
#define I2C_A_ADC_TRANS_MASK	0x00000010  	//Bit mask for I2c address DAC value
#define I2C_A_ADC_ABORT_MASK	0x00000020	//Bit mask for I2C transaction abort flag
#define I2C_A_ADC_LAST_MASK	0x00000040	//Bit mask for Last word transaction
#define I2C_A_ADC_BYTE_MASK	0x00000080	//Bit mask for Byte Mode

#define I2C_A_ADC_ADD		0x00000034	//This is the Device address for ADC 
#define I2C_A_ADC_READ		0x00000001	//To perform a read operation
#define I2C_A_ADC_START		0x00000100	//Start I2C transaction
#define I2C_A_ADC_ABORT		0x00000200	//I2C transaction abort
#define I2C_A_ADC_LAST		0x00000400	//I2C last transaction
#define I2C_A_ADC_BYTE		0x00000800	//I2C one byte mode

#define I2C_D_ADC_REG_MASK	0xfe000000  	//ADC address register 
#define I2C_D_ADC_DAT_MASK	0x01ff0000  	//ADC data register

#define ADC_TIMEOUT		0x00000007	//ADC Timeout Clock Disable
#define ADC_IFC_CTRL		0x0000000b	//ADC Interface Control
#define ADC_MASTER		0x0000000c	//ADC Master Mode Control
#define ADC_POWER		0x0000000d	//ADC PowerDown Control
#define ADC_ATTEN_ADCL		0x0000000e	//ADC Attenuation ADCL
#define ADC_ATTEN_ADCR		0x0000000f	//ADC Attenuation ADCR
#define ADC_ALC_CTRL1		0x00000010	//ADC ALC Control 1
#define ADC_ALC_CTRL2		0x00000011	//ADC ALC Control 2
#define ADC_ALC_CTRL3		0x00000012	//ADC ALC Control 3
#define ADC_NOISE_CTRL		0x00000013	//ADC Noise Gate Control
#define ADC_LIMIT_CTRL		0x00000014	//ADC Limiter Control
#define ADC_MUX			0x00000015  	//ADC Mux offset

#if 0
/* FIXME: Not tested yet. */
#define ADC_GAIN_MASK		0x000000ff	//Mask for ADC Gain
#define ADC_ZERODB		0x000000cf	//Value to set ADC to 0dB
#define ADC_MUTE_MASK		0x000000c0	//Mask for ADC mute
#define ADC_MUTE		0x000000c0	//Value to mute ADC
#define ADC_OSR			0x00000008	//Mask for ADC oversample rate select
#define ADC_TIMEOUT_DISABLE	0x00000008	//Value and mask to disable Timeout clock
#define ADC_HPF_DISABLE		0x00000100	//Value and mask to disable High pass filter
#define ADC_TRANWIN_MASK	0x00000070	//Mask for Length of Transient Window
#endif

#define ADC_MUX_MASK		0x0000000f	//Mask for ADC Mux
#define ADC_MUX_PHONE		0x00000001	//Value to select TAD at ADC Mux (Not used)
#define ADC_MUX_MIC		0x00000002	//Value to select Mic at ADC Mux
#define ADC_MUX_LINEIN		0x00000004	//Value to select LineIn at ADC Mux
#define ADC_MUX_AUX		0x00000008	//Value to select Aux at ADC Mux

#define SET_CHANNEL 0  /* Testing channel outputs 0=Front, 1=Center/LFE, 2=Unknown, 3=Rear */
#define PCM_FRONT_CHANNEL 0
#define PCM_REAR_CHANNEL 1
#define PCM_CENTER_LFE_CHANNEL 2
#define PCM_UNKNOWN_CHANNEL 3
#define CONTROL_FRONT_CHANNEL 0
#define CONTROL_REAR_CHANNEL 3
#define CONTROL_CENTER_LFE_CHANNEL 1
#define CONTROL_UNKNOWN_CHANNEL 2


/* Based on WM8768 Datasheet Rev 4.2 page 32 */
#define SPI_REG_MASK	0x1ff	/* 16-bit SPI writes have a 7-bit address */
#define SPI_REG_SHIFT	9	/* followed by 9 bits of data */

#define SPI_LDA1_REG		0	/* digital attenuation */
#define SPI_RDA1_REG		1
#define SPI_LDA2_REG		4
#define SPI_RDA2_REG		5
#define SPI_LDA3_REG		6
#define SPI_RDA3_REG		7
#define SPI_LDA4_REG		13
#define SPI_RDA4_REG		14
#define SPI_MASTDA_REG		8

#define SPI_DA_BIT_UPDATE	(1<<8)	/* update attenuation values */
#define SPI_DA_BIT_0dB		0xff	/* 0 dB */
#define SPI_DA_BIT_infdB	0x00	/* inf dB attenuation (mute) */

#define SPI_PL_REG		2
#define SPI_PL_BIT_L_M		(0<<5)	/* left channel = mute */
#define SPI_PL_BIT_L_L		(1<<5)	/* left channel = left */
#define SPI_PL_BIT_L_R		(2<<5)	/* left channel = right */
#define SPI_PL_BIT_L_C		(3<<5)	/* left channel = (L+R)/2 */
#define SPI_PL_BIT_R_M		(0<<7)	/* right channel = mute */
#define SPI_PL_BIT_R_L		(1<<7)	/* right channel = left */
#define SPI_PL_BIT_R_R		(2<<7)	/* right channel = right */
#define SPI_PL_BIT_R_C		(3<<7)	/* right channel = (L+R)/2 */
#define SPI_IZD_REG		2
#define SPI_IZD_BIT		(1<<4)	/* infinite zero detect */

#define SPI_FMT_REG		3
#define SPI_FMT_BIT_RJ		(0<<0)	/* right justified mode */
#define SPI_FMT_BIT_LJ		(1<<0)	/* left justified mode */
#define SPI_FMT_BIT_I2S		(2<<0)	/* I2S mode */
#define SPI_FMT_BIT_DSP		(3<<0)	/* DSP Modes A or B */
#define SPI_LRP_REG		3
#define SPI_LRP_BIT		(1<<2)	/* invert LRCLK polarity */
#define SPI_BCP_REG		3
#define SPI_BCP_BIT		(1<<3)	/* invert BCLK polarity */
#define SPI_IWL_REG		3
#define SPI_IWL_BIT_16		(0<<4)	/* 16-bit world length */
#define SPI_IWL_BIT_20		(1<<4)	/* 20-bit world length */
#define SPI_IWL_BIT_24		(2<<4)	/* 24-bit world length */
#define SPI_IWL_BIT_32		(3<<4)	/* 32-bit world length */

#define SPI_MS_REG		10
#define SPI_MS_BIT		(1<<5)	/* master mode */
#define SPI_RATE_REG		10	/* only applies in master mode */
#define SPI_RATE_BIT_128	(0<<6)	/* MCLK = LRCLK * 128 */
#define SPI_RATE_BIT_192	(1<<6)
#define SPI_RATE_BIT_256	(2<<6)
#define SPI_RATE_BIT_384	(3<<6)
#define SPI_RATE_BIT_512	(4<<6)
#define SPI_RATE_BIT_768	(5<<6)

/* They really do label the bit for the 4th channel "4" and not "3" */
#define SPI_DMUTE0_REG		9
#define SPI_DMUTE1_REG		9
#define SPI_DMUTE2_REG		9
#define SPI_DMUTE4_REG		15
#define SPI_DMUTE0_BIT		(1<<3)
#define SPI_DMUTE1_BIT		(1<<4)
#define SPI_DMUTE2_BIT		(1<<5)
#define SPI_DMUTE4_BIT		(1<<2)

#define SPI_PHASE0_REG		3
#define SPI_PHASE1_REG		3
#define SPI_PHASE2_REG		3
#define SPI_PHASE4_REG		15
#define SPI_PHASE0_BIT		(1<<6)
#define SPI_PHASE1_BIT		(1<<7)
#define SPI_PHASE2_BIT		(1<<8)
#define SPI_PHASE4_BIT		(1<<3)

#define SPI_PDWN_REG		2	/* power down all DACs */
#define SPI_PDWN_BIT		(1<<2)
#define SPI_DACD0_REG		10	/* power down individual DACs */
#define SPI_DACD1_REG		10
#define SPI_DACD2_REG		10
#define SPI_DACD4_REG		15
#define SPI_DACD0_BIT		(1<<1)
#define SPI_DACD1_BIT		(1<<2)
#define SPI_DACD2_BIT		(1<<3)
#define SPI_DACD4_BIT		(1<<0)	/* datasheet error says it's 1 */

#define SPI_PWRDNALL_REG	10	/* power down everything */
#define SPI_PWRDNALL_BIT	(1<<4)

#include "ca_midi.h"

struct snd_ca0106;

struct snd_ca0106_channel {
	struct snd_ca0106 *emu;
	int number;
	int use;
	void (*interrupt)(struct snd_ca0106 *emu, struct snd_ca0106_channel *channel);
	struct snd_ca0106_pcm *epcm;
};

struct snd_ca0106_pcm {
	struct snd_ca0106 *emu;
	struct snd_pcm_substream *substream;
        int channel_id;
	unsigned short running;
};

struct snd_ca0106_details {
        u32 serial;
        char * name;
        int ac97;
	int gpio_type;
	int i2c_adc;
	int spi_dac;
};

// definition of the chip-specific record
struct snd_ca0106 {
	struct snd_card *card;
	struct snd_ca0106_details *details;
	struct pci_dev *pci;

	unsigned long port;
	struct resource *res_port;
	int irq;

	unsigned int serial;            /* serial number */
	unsigned short model;		/* subsystem id */

	spinlock_t emu_lock;

	struct snd_ac97 *ac97;
	struct snd_pcm *pcm;

	struct snd_ca0106_channel playback_channels[4];
	struct snd_ca0106_channel capture_channels[4];
	u32 spdif_bits[4];             /* s/pdif out setup */
	int spdif_enable;
	int capture_source;
	int i2c_capture_source;
	u8 i2c_capture_volume[4][2];
	int capture_mic_line_in;

	struct snd_dma_buffer buffer;

	struct snd_ca_midi midi;
	struct snd_ca_midi midi2;

	u16 spi_dac_reg[16];
};

int snd_ca0106_mixer(struct snd_ca0106 *emu);
int snd_ca0106_proc_init(struct snd_ca0106 * emu);

unsigned int snd_ca0106_ptr_read(struct snd_ca0106 * emu, 
				 unsigned int reg, 
				 unsigned int chn);

void snd_ca0106_ptr_write(struct snd_ca0106 *emu, 
			  unsigned int reg, 
			  unsigned int chn, 
			  unsigned int data);

int snd_ca0106_i2c_write(struct snd_ca0106 *emu, u32 reg, u32 value);

int snd_ca0106_spi_write(struct snd_ca0106 * emu,
				   unsigned int data);