mach64.h

来自「linux 内核源代码」· C头文件 代码 · 共 1,379 行 · 第 1/4 页

				 OVERLAY_EOF_INT_EN |	\
				 ONESHOT_CAP_INT_EN |	\
				 BUSMASTER_EOL_INT_EN |	\
				 GP_INT_EN |		\
				 SNAPSHOT2_INT_EN)

/* DAC control values */

#define DAC_EXT_SEL_RS2		0x01
#define DAC_EXT_SEL_RS3		0x02
#define DAC_8BIT_EN		0x00000100
#define DAC_PIX_DLY_MASK	0x00000600
#define DAC_PIX_DLY_0NS		0x00000000
#define DAC_PIX_DLY_2NS		0x00000200
#define DAC_PIX_DLY_4NS		0x00000400
#define DAC_BLANK_ADJ_MASK	0x00001800
#define DAC_BLANK_ADJ_0		0x00000000
#define DAC_BLANK_ADJ_1		0x00000800
#define DAC_BLANK_ADJ_2		0x00001000

/* DAC control values (my source XL/XC Register reference) */
#define DAC_OUTPUT_MASK         0x00000001  /* 0 - PAL, 1 - NTSC */
#define DAC_MISTERY_BIT         0x00000002  /* PS2 ? RS343 ?, EXTRA_BRIGHT for GT */
#define DAC_BLANKING            0x00000004
#define DAC_CMP_DISABLE         0x00000008
#define DAC1_CLK_SEL            0x00000010
#define PALETTE_ACCESS_CNTL     0x00000020
#define PALETTE2_SNOOP_EN       0x00000040
#define DAC_CMP_OUTPUT          0x00000080 /* read only */
/* #define DAC_8BIT_EN is ok */
#define CRT_SENSE               0x00000800 /* read only */
#define CRT_DETECTION_ON        0x00001000
#define DAC_VGA_ADR_EN          0x00002000
#define DAC_FEA_CON_EN          0x00004000
#define DAC_PDWN                0x00008000
#define DAC_TYPE_MASK           0x00070000 /* read only */



/* Mix control values */

#define MIX_NOT_DST		0x0000
#define MIX_0			0x0001
#define MIX_1			0x0002
#define MIX_DST			0x0003
#define MIX_NOT_SRC		0x0004
#define MIX_XOR			0x0005
#define MIX_XNOR		0x0006
#define MIX_SRC			0x0007
#define MIX_NAND		0x0008
#define MIX_NOT_SRC_OR_DST	0x0009
#define MIX_SRC_OR_NOT_DST	0x000a
#define MIX_OR			0x000b
#define MIX_AND			0x000c
#define MIX_SRC_AND_NOT_DST	0x000d
#define MIX_NOT_SRC_AND_DST	0x000e
#define MIX_NOR			0x000f

/* Maximum engine dimensions */
#define ENGINE_MIN_X		0
#define ENGINE_MIN_Y		0
#define ENGINE_MAX_X		4095
#define ENGINE_MAX_Y		16383

/* Mach64 engine bit constants - these are typically ORed together */

/* BUS_CNTL register constants */
#define BUS_APER_REG_DIS	0x00000010
#define BUS_FIFO_ERR_ACK	0x00200000
#define BUS_HOST_ERR_ACK	0x00800000

/* GEN_TEST_CNTL register constants */
#define GEN_OVR_OUTPUT_EN	0x20
#define HWCURSOR_ENABLE		0x80
#define GUI_ENGINE_ENABLE	0x100
#define BLOCK_WRITE_ENABLE	0x200

/* DSP_CONFIG register constants */
#define DSP_XCLKS_PER_QW	0x00003fff
#define DSP_LOOP_LATENCY	0x000f0000
#define DSP_PRECISION		0x00700000

/* DSP_ON_OFF register constants */
#define DSP_OFF			0x000007ff
#define DSP_ON			0x07ff0000
#define VGA_DSP_OFF		DSP_OFF
#define VGA_DSP_ON		DSP_ON
#define VGA_DSP_XCLKS_PER_QW	DSP_XCLKS_PER_QW

/* PLL register indices and fields */
#define MPLL_CNTL		0x00
#define PLL_PC_GAIN		0x07
#define PLL_VC_GAIN		0x18
#define PLL_DUTY_CYC		0xE0
#define VPLL_CNTL		0x01
#define PLL_REF_DIV		0x02
#define PLL_GEN_CNTL		0x03
#define PLL_OVERRIDE		0x01	/* PLL_SLEEP */
#define PLL_MCLK_RST		0x02	/* PLL_MRESET */
#define OSC_EN			0x04
#define EXT_CLK_EN		0x08
#define FORCE_DCLK_TRI_STATE	0x08    /* VT4 -> */
#define MCLK_SRC_SEL		0x70
#define EXT_CLK_CNTL		0x80
#define DLL_PWDN		0x80    /* VT4 -> */
#define MCLK_FB_DIV		0x04
#define PLL_VCLK_CNTL		0x05
#define PLL_VCLK_SRC_SEL	0x03
#define PLL_VCLK_RST		0x04
#define PLL_VCLK_INVERT		0x08
#define VCLK_POST_DIV		0x06
#define VCLK0_POST		0x03
#define VCLK1_POST		0x0C
#define VCLK2_POST		0x30
#define VCLK3_POST		0xC0
#define VCLK0_FB_DIV		0x07
#define VCLK1_FB_DIV		0x08
#define VCLK2_FB_DIV		0x09
#define VCLK3_FB_DIV		0x0A
#define PLL_EXT_CNTL		0x0B
#define PLL_XCLK_MCLK_RATIO	0x03
#define PLL_XCLK_SRC_SEL	0x07
#define PLL_MFB_TIMES_4_2B	0x08
#define PLL_VCLK0_XDIV		0x10
#define PLL_VCLK1_XDIV		0x20
#define PLL_VCLK2_XDIV		0x40
#define PLL_VCLK3_XDIV		0x80
#define DLL_CNTL		0x0C
#define DLL1_CNTL		0x0C
#define VFC_CNTL		0x0D
#define PLL_TEST_CNTL		0x0E
#define PLL_TEST_COUNT		0x0F
#define LVDS_CNTL0		0x10
#define LVDS_CNTL1		0x11
#define AGP1_CNTL		0x12
#define AGP2_CNTL		0x13
#define DLL2_CNTL		0x14
#define SCLK_FB_DIV		0x15
#define SPLL_CNTL1		0x16
#define SPLL_CNTL2		0x17
#define APLL_STRAPS		0x18
#define EXT_VPLL_CNTL		0x19
#define EXT_VPLL_EN		0x04
#define EXT_VPLL_VGA_EN		0x08
#define EXT_VPLL_INSYNC		0x10
#define EXT_VPLL_REF_DIV	0x1A
#define EXT_VPLL_FB_DIV		0x1B
#define EXT_VPLL_MSB		0x1C
#define HTOTAL_CNTL		0x1D
#define BYTE_CLK_CNTL		0x1E
#define TV_PLL_CNTL1		0x1F
#define TV_PLL_CNTL2		0x20
#define TV_PLL_CNTL		0x21
#define EXT_TV_PLL		0x22
#define V2PLL_CNTL		0x23
#define PLL_V2CLK_CNTL		0x24
#define EXT_V2PLL_REF_DIV	0x25
#define EXT_V2PLL_FB_DIV	0x26
#define EXT_V2PLL_MSB		0x27
#define HTOTAL2_CNTL		0x28
#define PLL_YCLK_CNTL		0x29
#define PM_DYN_CLK_CNTL		0x2A

/* CONFIG_CNTL register constants */
#define APERTURE_4M_ENABLE	1
#define APERTURE_8M_ENABLE	2
#define VGA_APERTURE_ENABLE	4

/* CONFIG_STAT0 register constants (GX, CX) */
#define CFG_BUS_TYPE		0x00000007
#define CFG_MEM_TYPE		0x00000038
#define CFG_INIT_DAC_TYPE	0x00000e00

/* CONFIG_STAT0 register constants (CT, ET, VT) */
#define CFG_MEM_TYPE_xT		0x00000007

#define ISA			0
#define EISA			1
#define LOCAL_BUS		6
#define PCI			7

/* Memory types for GX, CX */
#define DRAMx4			0
#define VRAMx16			1
#define VRAMx16ssr		2
#define DRAMx16			3
#define GraphicsDRAMx16		4
#define EnhancedVRAMx16		5
#define EnhancedVRAMx16ssr	6

/* Memory types for CT, ET, VT, GT */
#define DRAM			1
#define EDO			2
#define PSEUDO_EDO		3
#define SDRAM			4
#define SGRAM			5
#define WRAM			6
#define SDRAM32			6

#define DAC_INTERNAL		0x00
#define DAC_IBMRGB514		0x01
#define DAC_ATI68875		0x02
#define DAC_TVP3026_A		0x72
#define DAC_BT476		0x03
#define DAC_BT481		0x04
#define DAC_ATT20C491		0x14
#define DAC_SC15026		0x24
#define DAC_MU9C1880		0x34
#define DAC_IMSG174		0x44
#define DAC_ATI68860_B		0x05
#define DAC_ATI68860_C		0x15
#define DAC_TVP3026_B		0x75
#define DAC_STG1700		0x06
#define DAC_ATT498		0x16
#define DAC_STG1702		0x07
#define DAC_SC15021		0x17
#define DAC_ATT21C498		0x27
#define DAC_STG1703		0x37
#define DAC_CH8398		0x47
#define DAC_ATT20C408		0x57

#define CLK_ATI18818_0		0
#define CLK_ATI18818_1		1
#define CLK_STG1703		2
#define CLK_CH8398		3
#define CLK_INTERNAL		4
#define CLK_ATT20C408		5
#define CLK_IBMRGB514		6

/* MEM_CNTL register constants */
#define MEM_SIZE_ALIAS		0x00000007
#define MEM_SIZE_512K		0x00000000
#define MEM_SIZE_1M		0x00000001
#define MEM_SIZE_2M		0x00000002
#define MEM_SIZE_4M		0x00000003
#define MEM_SIZE_6M		0x00000004
#define MEM_SIZE_8M		0x00000005
#define MEM_SIZE_ALIAS_GTB	0x0000000F
#define MEM_SIZE_2M_GTB		0x00000003
#define MEM_SIZE_4M_GTB		0x00000007
#define MEM_SIZE_6M_GTB		0x00000009
#define MEM_SIZE_8M_GTB		0x0000000B
#define MEM_BNDRY		0x00030000
#define MEM_BNDRY_0K		0x00000000
#define MEM_BNDRY_256K		0x00010000
#define MEM_BNDRY_512K		0x00020000
#define MEM_BNDRY_1M		0x00030000
#define MEM_BNDRY_EN		0x00040000

#define ONE_MB			0x100000
/* ATI PCI constants */
#define PCI_ATI_VENDOR_ID	0x1002


/* CONFIG_CHIP_ID register constants */
#define CFG_CHIP_TYPE		0x0000FFFF
#define CFG_CHIP_CLASS		0x00FF0000
#define CFG_CHIP_REV		0xFF000000
#define CFG_CHIP_MAJOR		0x07000000
#define CFG_CHIP_FND_ID		0x38000000
#define CFG_CHIP_MINOR		0xC0000000


/* Chip IDs read from CONFIG_CHIP_ID */

/* mach64GX family */
#define GX_CHIP_ID	0xD7	/* mach64GX (ATI888GX00) */
#define CX_CHIP_ID	0x57	/* mach64CX (ATI888CX00) */

#define GX_PCI_ID	0x4758	/* mach64GX (ATI888GX00) */
#define CX_PCI_ID	0x4358	/* mach64CX (ATI888CX00) */

/* mach64CT family */
#define CT_CHIP_ID	0x4354	/* mach64CT (ATI264CT) */
#define ET_CHIP_ID	0x4554	/* mach64ET (ATI264ET) */

/* mach64CT family / mach64VT class */
#define VT_CHIP_ID	0x5654	/* mach64VT (ATI264VT) */
#define VU_CHIP_ID	0x5655	/* mach64VTB (ATI264VTB) */
#define VV_CHIP_ID	0x5656	/* mach64VT4 (ATI264VT4) */

/* mach64CT family / mach64GT (3D RAGE) class */
#define LB_CHIP_ID	0x4c42	/* RAGE LT PRO, AGP */
#define LD_CHIP_ID	0x4c44	/* RAGE LT PRO */
#define LG_CHIP_ID	0x4c47	/* RAGE LT */
#define LI_CHIP_ID	0x4c49	/* RAGE LT PRO */
#define LP_CHIP_ID	0x4c50	/* RAGE LT PRO */
#define LT_CHIP_ID	0x4c54	/* RAGE LT */

/* mach64CT family / (Rage XL) class */
#define GR_CHIP_ID	0x4752	/* RAGE XL, BGA, PCI33 */
#define GS_CHIP_ID	0x4753	/* RAGE XL, PQFP, PCI33 */
#define GM_CHIP_ID	0x474d	/* RAGE XL, BGA, AGP 1x,2x */
#define GN_CHIP_ID	0x474e	/* RAGE XL, PQFP,AGP 1x,2x */
#define GO_CHIP_ID	0x474f	/* RAGE XL, BGA, PCI66 */
#define GL_CHIP_ID	0x474c	/* RAGE XL, PQFP, PCI66 */

#define IS_XL(id) ((id)==GR_CHIP_ID || (id)==GS_CHIP_ID || \
		   (id)==GM_CHIP_ID || (id)==GN_CHIP_ID || \
		   (id)==GO_CHIP_ID || (id)==GL_CHIP_ID)

#define GT_CHIP_ID	0x4754	/* RAGE (GT) */
#define GU_CHIP_ID	0x4755	/* RAGE II/II+ (GTB) */
#define GV_CHIP_ID	0x4756	/* RAGE IIC, PCI */
#define GW_CHIP_ID	0x4757	/* RAGE IIC, AGP */
#define GZ_CHIP_ID	0x475a	/* RAGE IIC, AGP */
#define GB_CHIP_ID	0x4742	/* RAGE PRO, BGA, AGP 1x and 2x */
#define GD_CHIP_ID	0x4744	/* RAGE PRO, BGA, AGP 1x only */
#define GI_CHIP_ID	0x4749	/* RAGE PRO, BGA, PCI33 only */
#define GP_CHIP_ID	0x4750	/* RAGE PRO, PQFP, PCI33, full 3D */
#define GQ_CHIP_ID	0x4751	/* RAGE PRO, PQFP, PCI33, limited 3D */

#define LM_CHIP_ID	0x4c4d	/* RAGE Mobility AGP, full function */
#define LN_CHIP_ID	0x4c4e	/* RAGE Mobility AGP */
#define LR_CHIP_ID	0x4c52	/* RAGE Mobility PCI, full function */
#define LS_CHIP_ID	0x4c53	/* RAGE Mobility PCI */

#define IS_MOBILITY(id) ((id)==LM_CHIP_ID || (id)==LN_CHIP_ID || \
			(id)==LR_CHIP_ID || (id)==LS_CHIP_ID)
/* Mach64 major ASIC revisions */
#define MACH64_ASIC_NEC_VT_A3		0x08
#define MACH64_ASIC_NEC_VT_A4		0x48
#define MACH64_ASIC_SGS_VT_A4		0x40
#define MACH64_ASIC_SGS_VT_B1S1		0x01
#define MACH64_ASIC_SGS_GT_B1S1		0x01
#define MACH64_ASIC_SGS_GT_B1S2		0x41
#define MACH64_ASIC_UMC_GT_B2U1		0x1a
#define MACH64_ASIC_UMC_GT_B2U2		0x5a
#define MACH64_ASIC_UMC_VT_B2U3		0x9a
#define MACH64_ASIC_UMC_GT_B2U3		0x9a
#define MACH64_ASIC_UMC_R3B_D_P_A1	0x1b
#define MACH64_ASIC_UMC_R3B_D_P_A2	0x5b
#define MACH64_ASIC_UMC_R3B_D_P_A3	0x1c
#define MACH64_ASIC_UMC_R3B_D_P_A4	0x5c

/* Mach64 foundries */
#define MACH64_FND_SGS		0
#define MACH64_FND_NEC		1
#define MACH64_FND_UMC		3

/* Mach64 chip types */
#define MACH64_UNKNOWN		0
#define MACH64_GX		1
#define MACH64_CX		2
#define MACH64_CT		3Restore