📄 cdefbf561.h
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/* * File: include/asm-blackfin/mach-bf561/cdefBF561.h * Based on: * Author: * * Created: * Description: C POINTERS TO SYSTEM MMR REGISTER AND MEMORY MAP FOR ADSP-BF561 * * Rev: * * Modified: * * Bugs: Enter bugs at http://blackfin.uclinux.org/ * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2, or (at your option) * any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; see the file COPYING. * If not, write to the Free Software Foundation, * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */#ifndef _CDEF_BF561_H#define _CDEF_BF561_H#include <asm/blackfin.h>/* include all Core registers and bit definitions */#include "defBF561.h"/*include core specific register pointer definitions*/#include <asm/mach-common/cdef_LPBlackfin.h>#include <asm/system.h>/*********************************************************************************** *//* System MMR Register Map *//*********************************************************************************** *//* Clock and System Control (0xFFC00000 - 0xFFC000FF) */#define bfin_read_PLL_CTL() bfin_read16(PLL_CTL)#define bfin_write_PLL_CTL(val) bfin_write16(PLL_CTL,val)#define bfin_read_PLL_DIV() bfin_read16(PLL_DIV)#define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV,val)#define bfin_read_VR_CTL() bfin_read16(VR_CTL)/* Writing to VR_CTL initiates a PLL relock sequence. */static __inline__ void bfin_write_VR_CTL(unsigned int val){ unsigned long flags, iwr0, iwr1; /* Enable the PLL Wakeup bit in SIC IWR */ iwr0 = bfin_read32(SICA_IWR0); iwr1 = bfin_read32(SICA_IWR1); /* Only allow PPL Wakeup) */ bfin_write32(SICA_IWR0, IWR_ENABLE(0)); bfin_write32(SICA_IWR1, 0); bfin_write16(VR_CTL, val); SSYNC(); local_irq_save(flags); asm("IDLE;"); local_irq_restore(flags); bfin_write32(SICA_IWR0, iwr0); bfin_write32(SICA_IWR1, iwr1);}#define bfin_read_PLL_STAT() bfin_read16(PLL_STAT)#define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT,val)#define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT)#define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT,val)#define bfin_read_CHIPID() bfin_read32(CHIPID)/* For MMR's that are reserved on Core B, set up defines to better integrate with other ports */#define bfin_read_SWRST() bfin_read_SICA_SWRST()#define bfin_write_SWRST(val) bfin_write_SICA_SWRST(val)#define bfin_read_SYSCR() bfin_read_SICA_SYSCR()#define bfin_write_SYSCR(val) bfin_write_SICA_SYSCR(val)/* System Reset and Interrupt Controller registers for core A (0xFFC0 0100-0xFFC0 01FF) */#define bfin_read_SICA_SWRST() bfin_read16(SICA_SWRST)#define bfin_write_SICA_SWRST(val) bfin_write16(SICA_SWRST,val)#define bfin_read_SICA_SYSCR() bfin_read16(SICA_SYSCR)#define bfin_write_SICA_SYSCR(val) bfin_write16(SICA_SYSCR,val)#define bfin_read_SICA_RVECT() bfin_read16(SICA_RVECT)#define bfin_write_SICA_RVECT(val) bfin_write16(SICA_RVECT,val)#define bfin_read_SICA_IMASK() bfin_read32(SICA_IMASK)#define bfin_write_SICA_IMASK(val) bfin_write32(SICA_IMASK,val)#define bfin_read_SICA_IMASK0() bfin_read32(SICA_IMASK0)#define bfin_write_SICA_IMASK0(val) bfin_write32(SICA_IMASK0,val)#define bfin_read_SICA_IMASK1() bfin_read32(SICA_IMASK1)#define bfin_write_SICA_IMASK1(val) bfin_write32(SICA_IMASK1,val)#define bfin_read_SICA_IAR0() bfin_read32(SICA_IAR0)#define bfin_write_SICA_IAR0(val) bfin_write32(SICA_IAR0,val)#define bfin_read_SICA_IAR1() bfin_read32(SICA_IAR1)#define bfin_write_SICA_IAR1(val) bfin_write32(SICA_IAR1,val)#define bfin_read_SICA_IAR2() bfin_read32(SICA_IAR2)#define bfin_write_SICA_IAR2(val) bfin_write32(SICA_IAR2,val)#define bfin_read_SICA_IAR3() bfin_read32(SICA_IAR3)#define bfin_write_SICA_IAR3(val) bfin_write32(SICA_IAR3,val)#define bfin_read_SICA_IAR4() bfin_read32(SICA_IAR4)#define bfin_write_SICA_IAR4(val) bfin_write32(SICA_IAR4,val)#define bfin_read_SICA_IAR5() bfin_read32(SICA_IAR5)#define bfin_write_SICA_IAR5(val) bfin_write32(SICA_IAR5,val)#define bfin_read_SICA_IAR6() bfin_read32(SICA_IAR6)#define bfin_write_SICA_IAR6(val) bfin_write32(SICA_IAR6,val)#define bfin_read_SICA_IAR7() bfin_read32(SICA_IAR7)#define bfin_write_SICA_IAR7(val) bfin_write32(SICA_IAR7,val)#define bfin_read_SICA_ISR0() bfin_read32(SICA_ISR0)#define bfin_write_SICA_ISR0(val) bfin_write32(SICA_ISR0,val)#define bfin_read_SICA_ISR1() bfin_read32(SICA_ISR1)#define bfin_write_SICA_ISR1(val) bfin_write32(SICA_ISR1,val)#define bfin_read_SICA_IWR0() bfin_read32(SICA_IWR0)#define bfin_write_SICA_IWR0(val) bfin_write32(SICA_IWR0,val)#define bfin_read_SICA_IWR1() bfin_read32(SICA_IWR1)#define bfin_write_SICA_IWR1(val) bfin_write32(SICA_IWR1,val)/* System Reset and Interrupt Controller registers for Core B (0xFFC0 1100-0xFFC0 11FF) */#define bfin_read_SICB_SWRST() bfin_read16(SICB_SWRST)#define bfin_write_SICB_SWRST(val) bfin_write16(SICB_SWRST,val)#define bfin_read_SICB_SYSCR() bfin_read16(SICB_SYSCR)#define bfin_write_SICB_SYSCR(val) bfin_write16(SICB_SYSCR,val)#define bfin_read_SICB_RVECT() bfin_read16(SICB_RVECT)#define bfin_write_SICB_RVECT(val) bfin_write16(SICB_RVECT,val)#define bfin_read_SICB_IMASK0() bfin_read32(SICB_IMASK0)#define bfin_write_SICB_IMASK0(val) bfin_write32(SICB_IMASK0,val)#define bfin_read_SICB_IMASK1() bfin_read32(SICB_IMASK1)#define bfin_write_SICB_IMASK1(val) bfin_write32(SICB_IMASK1,val)#define bfin_read_SICB_IAR0() bfin_read32(SICB_IAR0)#define bfin_write_SICB_IAR0(val) bfin_write32(SICB_IAR0,val)#define bfin_read_SICB_IAR1() bfin_read32(SICB_IAR1)#define bfin_write_SICB_IAR1(val) bfin_write32(SICB_IAR1,val)#define bfin_read_SICB_IAR2() bfin_read32(SICB_IAR2)#define bfin_write_SICB_IAR2(val) bfin_write32(SICB_IAR2,val)#define bfin_read_SICB_IAR3() bfin_read32(SICB_IAR3)#define bfin_write_SICB_IAR3(val) bfin_write32(SICB_IAR3,val)#define bfin_read_SICB_IAR4() bfin_read32(SICB_IAR4)#define bfin_write_SICB_IAR4(val) bfin_write32(SICB_IAR4,val)#define bfin_read_SICB_IAR5() bfin_read32(SICB_IAR5)#define bfin_write_SICB_IAR5(val) bfin_write32(SICB_IAR5,val)#define bfin_read_SICB_IAR6() bfin_read32(SICB_IAR6)#define bfin_write_SICB_IAR6(val) bfin_write32(SICB_IAR6,val)#define bfin_read_SICB_IAR7() bfin_read32(SICB_IAR7)#define bfin_write_SICB_IAR7(val) bfin_write32(SICB_IAR7,val)#define bfin_read_SICB_ISR0() bfin_read32(SICB_ISR0)#define bfin_write_SICB_ISR0(val) bfin_write32(SICB_ISR0,val)#define bfin_read_SICB_ISR1() bfin_read32(SICB_ISR1)#define bfin_write_SICB_ISR1(val) bfin_write32(SICB_ISR1,val)#define bfin_read_SICB_IWR0() bfin_read32(SICB_IWR0)#define bfin_write_SICB_IWR0(val) bfin_write32(SICB_IWR0,val)#define bfin_read_SICB_IWR1() bfin_read32(SICB_IWR1)#define bfin_write_SICB_IWR1(val) bfin_write32(SICB_IWR1,val)/* Watchdog Timer registers for Core A (0xFFC0 0200-0xFFC0 02FF) */#define bfin_read_WDOGA_CTL() bfin_read16(WDOGA_CTL)#define bfin_write_WDOGA_CTL(val) bfin_write16(WDOGA_CTL,val)#define bfin_read_WDOGA_CNT() bfin_read32(WDOGA_CNT)#define bfin_write_WDOGA_CNT(val) bfin_write32(WDOGA_CNT,val)#define bfin_read_WDOGA_STAT() bfin_read32(WDOGA_STAT)#define bfin_write_WDOGA_STAT(val) bfin_write32(WDOGA_STAT,val)/* Watchdog Timer registers for Core B (0xFFC0 1200-0xFFC0 12FF) */#define bfin_read_WDOGB_CTL() bfin_read16(WDOGB_CTL)#define bfin_write_WDOGB_CTL(val) bfin_write16(WDOGB_CTL,val)#define bfin_read_WDOGB_CNT() bfin_read32(WDOGB_CNT)#define bfin_write_WDOGB_CNT(val) bfin_write32(WDOGB_CNT,val)#define bfin_read_WDOGB_STAT() bfin_read32(WDOGB_STAT)#define bfin_write_WDOGB_STAT(val) bfin_write32(WDOGB_STAT,val)/* UART Controller (0xFFC00400 - 0xFFC004FF) */#define bfin_read_UART_THR() bfin_read16(UART_THR)#define bfin_write_UART_THR(val) bfin_write16(UART_THR,val)#define bfin_read_UART_RBR() bfin_read16(UART_RBR)#define bfin_write_UART_RBR(val) bfin_write16(UART_RBR,val)#define bfin_read_UART_DLL() bfin_read16(UART_DLL)#define bfin_write_UART_DLL(val) bfin_write16(UART_DLL,val)#define bfin_read_UART_IER() bfin_read16(UART_IER)#define bfin_write_UART_IER(val) bfin_write16(UART_IER,val)#define bfin_read_UART_DLH() bfin_read16(UART_DLH)#define bfin_write_UART_DLH(val) bfin_write16(UART_DLH,val)⌨️ 快捷键说明
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