cdefbf534.h

来自「linux 内核源代码」· C头文件 代码 · 共 954 行 · 第 1/5 页

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#define bfin_write_SPORT1_MRCS2(val)         bfin_write32(SPORT1_MRCS2,val)#define bfin_read_SPORT1_MRCS3()             bfin_read32(SPORT1_MRCS3)#define bfin_write_SPORT1_MRCS3(val)         bfin_write32(SPORT1_MRCS3,val)/* External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF)							*/#define bfin_read_EBIU_AMGCTL()              bfin_read16(EBIU_AMGCTL)#define bfin_write_EBIU_AMGCTL(val)          bfin_write16(EBIU_AMGCTL,val)#define bfin_read_EBIU_AMBCTL0()             bfin_read32(EBIU_AMBCTL0)#define bfin_write_EBIU_AMBCTL0(val)         bfin_write32(EBIU_AMBCTL0,val)#define bfin_read_EBIU_AMBCTL1()             bfin_read32(EBIU_AMBCTL1)#define bfin_write_EBIU_AMBCTL1(val)         bfin_write32(EBIU_AMBCTL1,val)#define bfin_read_EBIU_SDGCTL()              bfin_read32(EBIU_SDGCTL)#define bfin_write_EBIU_SDGCTL(val)          bfin_write32(EBIU_SDGCTL,val)#define bfin_read_EBIU_SDBCTL()              bfin_read16(EBIU_SDBCTL)#define bfin_write_EBIU_SDBCTL(val)          bfin_write16(EBIU_SDBCTL,val)#define bfin_read_EBIU_SDRRC()               bfin_read16(EBIU_SDRRC)#define bfin_write_EBIU_SDRRC(val)           bfin_write16(EBIU_SDRRC,val)#define bfin_read_EBIU_SDSTAT()              bfin_read16(EBIU_SDSTAT)#define bfin_write_EBIU_SDSTAT(val)          bfin_write16(EBIU_SDSTAT,val)/* DMA Traffic Control Registers													*/#define bfin_read_DMA_TC_PER()                bfin_read16(DMA_TC_PER)#define bfin_write_DMA_TC_PER(val)            bfin_write16(DMA_TC_PER,val)#define bfin_read_DMA_TC_CNT()                bfin_read16(DMA_TC_CNT)#define bfin_write_DMA_TC_CNT(val)            bfin_write16(DMA_TC_CNT,val)/* Alternate deprecated register names (below) provided for backwards code compatibility */#define bfin_read_DMA_TCPER()                bfin_read16(DMA_TCPER)#define bfin_write_DMA_TCPER(val)            bfin_write16(DMA_TCPER,val)#define bfin_read_DMA_TCCNT()                bfin_read16(DMA_TCCNT)#define bfin_write_DMA_TCCNT(val)            bfin_write16(DMA_TCCNT,val)/* DMA Controller																	*/#define bfin_read_DMA0_CONFIG()              bfin_read16(DMA0_CONFIG)#define bfin_write_DMA0_CONFIG(val)          bfin_write16(DMA0_CONFIG,val)#define bfin_read_DMA0_NEXT_DESC_PTR()       bfin_read32(DMA0_NEXT_DESC_PTR)#define bfin_write_DMA0_NEXT_DESC_PTR(val)   bfin_write32(DMA0_NEXT_DESC_PTR,val)#define bfin_read_DMA0_START_ADDR()          bfin_read32(DMA0_START_ADDR)#define bfin_write_DMA0_START_ADDR(val)      bfin_write32(DMA0_START_ADDR,val)#define bfin_read_DMA0_X_COUNT()             bfin_read16(DMA0_X_COUNT)#define bfin_write_DMA0_X_COUNT(val)         bfin_write16(DMA0_X_COUNT,val)#define bfin_read_DMA0_Y_COUNT()             bfin_read16(DMA0_Y_COUNT)#define bfin_write_DMA0_Y_COUNT(val)         bfin_write16(DMA0_Y_COUNT,val)#define bfin_read_DMA0_X_MODIFY()            bfin_read16(DMA0_X_MODIFY)#define bfin_write_DMA0_X_MODIFY(val)        bfin_write16(DMA0_X_MODIFY,val)#define bfin_read_DMA0_Y_MODIFY()            bfin_read16(DMA0_Y_MODIFY)#define bfin_write_DMA0_Y_MODIFY(val)        bfin_write16(DMA0_Y_MODIFY,val)#define bfin_read_DMA0_CURR_DESC_PTR()       bfin_read32(DMA0_CURR_DESC_PTR)#define bfin_write_DMA0_CURR_DESC_PTR(val)   bfin_write32(DMA0_CURR_DESC_PTR,val)#define bfin_read_DMA0_CURR_ADDR()           bfin_read32(DMA0_CURR_ADDR)#define bfin_write_DMA0_CURR_ADDR(val)       bfin_write32(DMA0_CURR_ADDR,val)#define bfin_read_DMA0_CURR_X_COUNT()        bfin_read16(DMA0_CURR_X_COUNT)#define bfin_write_DMA0_CURR_X_COUNT(val)    bfin_write16(DMA0_CURR_X_COUNT,val)#define bfin_read_DMA0_CURR_Y_COUNT()        bfin_read16(DMA0_CURR_Y_COUNT)#define bfin_write_DMA0_CURR_Y_COUNT(val)    bfin_write16(DMA0_CURR_Y_COUNT,val)#define bfin_read_DMA0_IRQ_STATUS()          bfin_read16(DMA0_IRQ_STATUS)#define bfin_write_DMA0_IRQ_STATUS(val)      bfin_write16(DMA0_IRQ_STATUS,val)#define bfin_read_DMA0_PERIPHERAL_MAP()      bfin_read16(DMA0_PERIPHERAL_MAP)#define bfin_write_DMA0_PERIPHERAL_MAP(val)  bfin_write16(DMA0_PERIPHERAL_MAP,val)#define bfin_read_DMA1_CONFIG()              bfin_read16(DMA1_CONFIG)#define bfin_write_DMA1_CONFIG(val)          bfin_write16(DMA1_CONFIG,val)#define bfin_read_DMA1_NEXT_DESC_PTR()       bfin_read32(DMA1_NEXT_DESC_PTR)#define bfin_write_DMA1_NEXT_DESC_PTR(val)   bfin_write32(DMA1_NEXT_DESC_PTR,val)#define bfin_read_DMA1_START_ADDR()          bfin_read32(DMA1_START_ADDR)#define bfin_write_DMA1_START_ADDR(val)      bfin_write32(DMA1_START_ADDR,val)#define bfin_read_DMA1_X_COUNT()             bfin_read16(DMA1_X_COUNT)#define bfin_write_DMA1_X_COUNT(val)         bfin_write16(DMA1_X_COUNT,val)#define bfin_read_DMA1_Y_COUNT()             bfin_read16(DMA1_Y_COUNT)#define bfin_write_DMA1_Y_COUNT(val)         bfin_write16(DMA1_Y_COUNT,val)#define bfin_read_DMA1_X_MODIFY()            bfin_read16(DMA1_X_MODIFY)#define bfin_write_DMA1_X_MODIFY(val)        bfin_write16(DMA1_X_MODIFY,val)#define bfin_read_DMA1_Y_MODIFY()            bfin_read16(DMA1_Y_MODIFY)#define bfin_write_DMA1_Y_MODIFY(val)        bfin_write16(DMA1_Y_MODIFY,val)#define bfin_read_DMA1_CURR_DESC_PTR()       bfin_read32(DMA1_CURR_DESC_PTR)#define bfin_write_DMA1_CURR_DESC_PTR(val)   bfin_write32(DMA1_CURR_DESC_PTR,val)#define bfin_read_DMA1_CURR_ADDR()           bfin_read32(DMA1_CURR_ADDR)#define bfin_write_DMA1_CURR_ADDR(val)       bfin_write32(DMA1_CURR_ADDR,val)#define bfin_read_DMA1_CURR_X_COUNT()        bfin_read16(DMA1_CURR_X_COUNT)#define bfin_write_DMA1_CURR_X_COUNT(val)    bfin_write16(DMA1_CURR_X_COUNT,val)#define bfin_read_DMA1_CURR_Y_COUNT()        bfin_read16(DMA1_CURR_Y_COUNT)#define bfin_write_DMA1_CURR_Y_COUNT(val)    bfin_write16(DMA1_CURR_Y_COUNT,val)#define bfin_read_DMA1_IRQ_STATUS()          bfin_read16(DMA1_IRQ_STATUS)#define bfin_write_DMA1_IRQ_STATUS(val)      bfin_write16(DMA1_IRQ_STATUS,val)#define bfin_read_DMA1_PERIPHERAL_MAP()      bfin_read16(DMA1_PERIPHERAL_MAP)#define bfin_write_DMA1_PERIPHERAL_MAP(val)  bfin_write16(DMA1_PERIPHERAL_MAP,val)#define bfin_read_DMA2_CONFIG()              bfin_read16(DMA2_CONFIG)#define bfin_write_DMA2_CONFIG(val)          bfin_write16(DMA2_CONFIG,val)#define bfin_read_DMA2_NEXT_DESC_PTR()       bfin_read32(DMA2_NEXT_DESC_PTR)#define bfin_write_DMA2_NEXT_DESC_PTR(val)   bfin_write32(DMA2_NEXT_DESC_PTR,val)#define bfin_read_DMA2_START_ADDR()          bfin_read32(DMA2_START_ADDR)#define bfin_write_DMA2_START_ADDR(val)      bfin_write32(DMA2_START_ADDR,val)#define bfin_read_DMA2_X_COUNT()             bfin_read16(DMA2_X_COUNT)#define bfin_write_DMA2_X_COUNT(val)         bfin_write16(DMA2_X_COUNT,val)#define bfin_read_DMA2_Y_COUNT()             bfin_read16(DMA2_Y_COUNT)#define bfin_write_DMA2_Y_COUNT(val)         bfin_write16(DMA2_Y_COUNT,val)#define bfin_read_DMA2_X_MODIFY()            bfin_read16(DMA2_X_MODIFY)#define bfin_write_DMA2_X_MODIFY(val)        bfin_write16(DMA2_X_MODIFY,val)#define bfin_read_DMA2_Y_MODIFY()            bfin_read16(DMA2_Y_MODIFY)#define bfin_write_DMA2_Y_MODIFY(val)        bfin_write16(DMA2_Y_MODIFY,val)#define bfin_read_DMA2_CURR_DESC_PTR()       bfin_read32(DMA2_CURR_DESC_PTR)#define bfin_write_DMA2_CURR_DESC_PTR(val)   bfin_write32(DMA2_CURR_DESC_PTR,val)#define bfin_read_DMA2_CURR_ADDR()           bfin_read32(DMA2_CURR_ADDR)#define bfin_write_DMA2_CURR_ADDR(val)       bfin_write32(DMA2_CURR_ADDR,val)#define bfin_read_DMA2_CURR_X_COUNT()        bfin_read16(DMA2_CURR_X_COUNT)#define bfin_write_DMA2_CURR_X_COUNT(val)    bfin_write16(DMA2_CURR_X_COUNT,val)#define bfin_read_DMA2_CURR_Y_COUNT()        bfin_read16(DMA2_CURR_Y_COUNT)#define bfin_write_DMA2_CURR_Y_COUNT(val)    bfin_write16(DMA2_CURR_Y_COUNT,val)#define bfin_read_DMA2_IRQ_STATUS()          bfin_read16(DMA2_IRQ_STATUS)#define bfin_write_DMA2_IRQ_STATUS(val)      bfin_write16(DMA2_IRQ_STATUS,val)#define bfin_read_DMA2_PERIPHERAL_MAP()      bfin_read16(DMA2_PERIPHERAL_MAP)#define bfin_write_DMA2_PERIPHERAL_MAP(val)  bfin_write16(DMA2_PERIPHERAL_MAP,val)#define bfin_read_DMA3_CONFIG()              bfin_read16(DMA3_CONFIG)#define bfin_write_DMA3_CONFIG(val)          bfin_write16(DMA3_CONFIG,val)#define bfin_read_DMA3_NEXT_DESC_PTR()       bfin_read32(DMA3_NEXT_DESC_PTR)#define bfin_write_DMA3_NEXT_DESC_PTR(val)   bfin_write32(DMA3_NEXT_DESC_PTR,val)#define bfin_read_DMA3_START_ADDR()          bfin_read32(DMA3_START_ADDR)#define bfin_write_DMA3_START_ADDR(val)      bfin_write32(DMA3_START_ADDR,val)#define bfin_read_DMA3_X_COUNT()             bfin_read16(DMA3_X_COUNT)#define bfin_write_DMA3_X_COUNT(val)         bfin_write16(DMA3_X_COUNT,val)#define bfin_read_DMA3_Y_COUNT()             bfin_read16(DMA3_Y_COUNT)#define bfin_write_DMA3_Y_COUNT(val)         bfin_write16(DMA3_Y_COUNT,val)#define bfin_read_DMA3_X_MODIFY()            bfin_read16(DMA3_X_MODIFY)#define bfin_write_DMA3_X_MODIFY(val)        bfin_write16(DMA3_X_MODIFY,val)#define bfin_read_DMA3_Y_MODIFY()            bfin_read16(DMA3_Y_MODIFY)#define bfin_write_DMA3_Y_MODIFY(val)        bfin_write16(DMA3_Y_MODIFY,val)#define bfin_read_DMA3_CURR_DESC_PTR()       bfin_read32(DMA3_CURR_DESC_PTR)#define bfin_write_DMA3_CURR_DESC_PTR(val)   bfin_write32(DMA3_CURR_DESC_PTR,val)#define bfin_read_DMA3_CURR_ADDR()           bfin_read32(DMA3_CURR_ADDR)#define bfin_write_DMA3_CURR_ADDR(val)       bfin_write32(DMA3_CURR_ADDR,val)#define bfin_read_DMA3_CURR_X_COUNT()        bfin_read16(DMA3_CURR_X_COUNT)#define bfin_write_DMA3_CURR_X_COUNT(val)    bfin_write16(DMA3_CURR_X_COUNT,val)#define bfin_read_DMA3_CURR_Y_COUNT()        bfin_read16(DMA3_CURR_Y_COUNT)#define bfin_write_DMA3_CURR_Y_COUNT(val)    bfin_write16(DMA3_CURR_Y_COUNT,val)#define bfin_read_DMA3_IRQ_STATUS()          bfin_read16(DMA3_IRQ_STATUS)#define bfin_write_DMA3_IRQ_STATUS(val)      bfin_write16(DMA3_IRQ_STATUS,val)#define bfin_read_DMA3_PERIPHERAL_MAP()      bfin_read16(DMA3_PERIPHERAL_MAP)#define bfin_write_DMA3_PERIPHERAL_MAP(val)  bfin_write16(DMA3_PERIPHERAL_MAP,val)#define bfin_read_DMA4_CONFIG()              bfin_read16(DMA4_CONFIG)#define bfin_write_DMA4_CONFIG(val)          bfin_write16(DMA4_CONFIG,val)#define bfin_read_DMA4_NEXT_DESC_PTR()       bfin_read32(DMA4_NEXT_DESC_PTR)#define bfin_write_DMA4_NEXT_DESC_PTR(val)   bfin_write32(DMA4_NEXT_DESC_PTR,val)#define bfin_read_DMA4_START_ADDR()          bfin_read32(DMA4_START_ADDR)#define bfin_write_DMA4_START_ADDR(val)      bfin_write32(DMA4_START_ADDR,val)#define bfin_read_DMA4_X_COUNT()             bfin_read16(DMA4_X_COUNT)#define bfin_write_DMA4_X_COUNT(val)         bfin_write16(DMA4_X_COUNT,val)#define bfin_read_DMA4_Y_COUNT()             bfin_read16(DMA4_Y_COUNT)#define bfin_write_DMA4_Y_COUNT(val)         bfin_write16(DMA4_Y_COUNT,val)#define bfin_read_DMA4_X_MODIFY()            bfin_read16(DMA4_X_MODIFY)#define bfin_write_DMA4_X_MODIFY(val)        bfin_write16(DMA4_X_MODIFY,val)#define bfin_read_DMA4_Y_MODIFY()            bfin_read16(DMA4_Y_MODIFY)#define bfin_write_DMA4_Y_MODIFY(val)        bfin_write16(DMA4_Y_MODIFY,val)#define bfin_read_DMA4_CURR_DESC_PTR()       bfin_read32(DMA4_CURR_DESC_PTR)#define bfin_write_DMA4_CURR_DESC_PTR(val)   bfin_write32(DMA4_CURR_DESC_PTR,val)#define bfin_read_DMA4_CURR_ADDR()           bfin_read32(DMA4_CURR_ADDR)#define bfin_write_DMA4_CURR_ADDR(val)       bfin_write32(DMA4_CURR_ADDR,val)#define bfin_read_DMA4_CURR_X_COUNT()        bfin_read16(DMA4_CURR_X_COUNT)#define bfin_write_DMA4_CURR_X_COUNT(val)    bfin_write16(DMA4_CURR_X_COUNT,val)#define bfin_read_DMA4_CURR_Y_COUNT()        bfin_read16(DMA4_CURR_Y_COUNT)#define bfin_write_DMA4_CURR_Y_COUNT(val)    bfin_write16(DMA4_CURR_Y_COUNT,val)#define bfin_read_DMA4_IRQ_STATUS()          bfin_read16(DMA4_IRQ_STATUS)#define bfin_write_DMA4_IRQ_STATUS(val)      bfin_write16(DMA4_IRQ_STATUS,val)#define bfin_read_DMA4_PERIPHERAL_MAP()      bfin_read16(DMA4_PERIPHERAL_MAP)#define bfin_write_DMA4_PERIPHERAL_MAP(val)  bfin_write16(DMA4_PERIPHERAL_MAP,val)#define bfin_read_DMA5_CONFIG()              bfin_read16(DMA5_CONFIG)#define bfin_write_DMA5_CONFIG(val)          bfin_write16(DMA5_CONFIG,val)#define bfin_read_DMA5_NEXT_DESC_PTR()       bfin_read32(DMA5_NEXT_DESC_PTR)#define bfin_write_DMA5_NEXT_DESC_PTR(val)   bfin_write32(DMA5_NEXT_DESC_PTR,val)#define bfin_read_DMA5_START_ADDR()          bfin_read32(DMA5_START_ADDR)#define bfin_write_DMA5_START_ADDR(val)      bfin_write32(DMA5_START_ADDR,val)#define bfin_read_DMA5_X_COUNT()             bfin_read16(DMA5_X_COUNT)#define bfin_write_DMA5_X_COUNT(val)         bfin_write16(DMA5_X_COUNT,val)#define bfin_read_DMA5_Y_COUNT()             bfin_read16(DMA5_Y_COUNT)#define bfin_write_DMA5_Y_COUNT(val)         bfin_write16(DMA5_Y_COUNT,val)#define bfin_read_DMA5_X_MODIFY()            bfin_read16(DMA5_X_MODIFY)#define bfin_write_DMA5_X_MODIFY(val)        bfin_write16(DMA5_X_MODIFY,val)#define bfin_read_DMA5_Y_MODIFY()            bfin_read16(DMA5_Y_MODIFY)#define bfin_write_DMA5_Y_MODIFY(val)        bfin_write16(DMA5_Y_MODIFY,val)#define bfin_read_DMA5_CURR_DESC_PTR()       bfin_read32(DMA5_CURR_DESC_PTR)#define bfin_write_DMA5_CURR_DESC_PTR(val)   bfin_write32(DMA5_CURR_DESC_PTR,val)#define bfin_read_DMA5_CURR_ADDR()           bfin_read32(DMA5_CURR_ADDR)#define bfin_write_DMA5_CURR_ADDR(val)       bfin_write32(DMA5_CURR_ADDR,val)#define bfin_read_DMA5_CURR_X_COUNT()        bfin_read16(DMA5_CURR_X_COUNT)#define bfin_write_DMA5_CURR_X_COUNT(val)    bfin_write16(DMA5_CURR_X_COUNT,val)#define bfin_read_DMA5_CURR_Y_COUNT()        bfin_read16(DMA5_CURR_Y_COUNT)#define bfin_write_DMA5_CURR_Y_COUNT(val)    bfin_write16(DMA5_CURR_Y_COUNT,val)#define bfin_read_DMA5_IRQ_STATUS()          bfin_read16(DMA5_IRQ_STATUS)
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