defbf534.h
来自「linux 内核源代码」· C头文件 代码 · 共 762 行 · 第 1/5 页
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762 行
#define TWI0_REGBASE 0xFFC01400#define TWI_CLKDIV 0xFFC01400 /* Serial Clock Divider Register */#define TWI_CONTROL 0xFFC01404 /* TWI Control Register */#define TWI_SLAVE_CTL 0xFFC01408 /* Slave Mode Control Register */#define TWI_SLAVE_STAT 0xFFC0140C /* Slave Mode Status Register */#define TWI_SLAVE_ADDR 0xFFC01410 /* Slave Mode Address Register */#define TWI_MASTER_CTL 0xFFC01414 /* Master Mode Control Register */#define TWI_MASTER_STAT 0xFFC01418 /* Master Mode Status Register */#define TWI_MASTER_ADDR 0xFFC0141C /* Master Mode Address Register */#define TWI_INT_STAT 0xFFC01420 /* TWI Interrupt Status Register */#define TWI_INT_MASK 0xFFC01424 /* TWI Master Interrupt Mask Register */#define TWI_FIFO_CTL 0xFFC01428 /* FIFO Control Register */#define TWI_FIFO_STAT 0xFFC0142C /* FIFO Status Register */#define TWI_XMT_DATA8 0xFFC01480 /* FIFO Transmit Data Single Byte Register */#define TWI_XMT_DATA16 0xFFC01484 /* FIFO Transmit Data Double Byte Register */#define TWI_RCV_DATA8 0xFFC01488 /* FIFO Receive Data Single Byte Register */#define TWI_RCV_DATA16 0xFFC0148C /* FIFO Receive Data Double Byte Register *//* General Purpose I/O Port G (0xFFC01500 - 0xFFC015FF) */#define PORTGIO 0xFFC01500 /* Port G I/O Pin State Specify Register */#define PORTGIO_CLEAR 0xFFC01504 /* Port G I/O Peripheral Interrupt Clear Register */#define PORTGIO_SET 0xFFC01508 /* Port G I/O Peripheral Interrupt Set Register */#define PORTGIO_TOGGLE 0xFFC0150C /* Port G I/O Pin State Toggle Register */#define PORTGIO_MASKA 0xFFC01510 /* Port G I/O Mask State Specify Interrupt A Register */#define PORTGIO_MASKA_CLEAR 0xFFC01514 /* Port G I/O Mask Disable Interrupt A Register */#define PORTGIO_MASKA_SET 0xFFC01518 /* Port G I/O Mask Enable Interrupt A Register */#define PORTGIO_MASKA_TOGGLE 0xFFC0151C /* Port G I/O Mask Toggle Enable Interrupt A Register */#define PORTGIO_MASKB 0xFFC01520 /* Port G I/O Mask State Specify Interrupt B Register */#define PORTGIO_MASKB_CLEAR 0xFFC01524 /* Port G I/O Mask Disable Interrupt B Register */#define PORTGIO_MASKB_SET 0xFFC01528 /* Port G I/O Mask Enable Interrupt B Register */#define PORTGIO_MASKB_TOGGLE 0xFFC0152C /* Port G I/O Mask Toggle Enable Interrupt B Register */#define PORTGIO_DIR 0xFFC01530 /* Port G I/O Direction Register */#define PORTGIO_POLAR 0xFFC01534 /* Port G I/O Source Polarity Register */#define PORTGIO_EDGE 0xFFC01538 /* Port G I/O Source Sensitivity Register */#define PORTGIO_BOTH 0xFFC0153C /* Port G I/O Set on BOTH Edges Register */#define PORTGIO_INEN 0xFFC01540 /* Port G I/O Input Enable Register *//* General Purpose I/O Port H (0xFFC01700 - 0xFFC017FF) */#define PORTHIO 0xFFC01700 /* Port H I/O Pin State Specify Register */#define PORTHIO_CLEAR 0xFFC01704 /* Port H I/O Peripheral Interrupt Clear Register */#define PORTHIO_SET 0xFFC01708 /* Port H I/O Peripheral Interrupt Set Register */#define PORTHIO_TOGGLE 0xFFC0170C /* Port H I/O Pin State Toggle Register */#define PORTHIO_MASKA 0xFFC01710 /* Port H I/O Mask State Specify Interrupt A Register */#define PORTHIO_MASKA_CLEAR 0xFFC01714 /* Port H I/O Mask Disable Interrupt A Register */#define PORTHIO_MASKA_SET 0xFFC01718 /* Port H I/O Mask Enable Interrupt A Register */#define PORTHIO_MASKA_TOGGLE 0xFFC0171C /* Port H I/O Mask Toggle Enable Interrupt A Register */#define PORTHIO_MASKB 0xFFC01720 /* Port H I/O Mask State Specify Interrupt B Register */#define PORTHIO_MASKB_CLEAR 0xFFC01724 /* Port H I/O Mask Disable Interrupt B Register */#define PORTHIO_MASKB_SET 0xFFC01728 /* Port H I/O Mask Enable Interrupt B Register */#define PORTHIO_MASKB_TOGGLE 0xFFC0172C /* Port H I/O Mask Toggle Enable Interrupt B Register */#define PORTHIO_DIR 0xFFC01730 /* Port H I/O Direction Register */#define PORTHIO_POLAR 0xFFC01734 /* Port H I/O Source Polarity Register */#define PORTHIO_EDGE 0xFFC01738 /* Port H I/O Source Sensitivity Register */#define PORTHIO_BOTH 0xFFC0173C /* Port H I/O Set on BOTH Edges Register */#define PORTHIO_INEN 0xFFC01740 /* Port H I/O Input Enable Register *//* UART1 Controller (0xFFC02000 - 0xFFC020FF) */#define UART1_THR 0xFFC02000 /* Transmit Holding register */#define UART1_RBR 0xFFC02000 /* Receive Buffer register */#define UART1_DLL 0xFFC02000 /* Divisor Latch (Low-Byte) */#define UART1_IER 0xFFC02004 /* Interrupt Enable Register */#define UART1_DLH 0xFFC02004 /* Divisor Latch (High-Byte) */#define UART1_IIR 0xFFC02008 /* Interrupt Identification Register */#define UART1_LCR 0xFFC0200C /* Line Control Register */#define UART1_MCR 0xFFC02010 /* Modem Control Register */#define UART1_LSR 0xFFC02014 /* Line Status Register */#define UART1_MSR 0xFFC02018 /* Modem Status Register */#define UART1_SCR 0xFFC0201C /* SCR Scratch Register */#define UART1_GCTL 0xFFC02024 /* Global Control Register *//* CAN Controller (0xFFC02A00 - 0xFFC02FFF) *//* For Mailboxes 0-15 */#define CAN_MC1 0xFFC02A00 /* Mailbox config reg 1 */#define CAN_MD1 0xFFC02A04 /* Mailbox direction reg 1 */#define CAN_TRS1 0xFFC02A08 /* Transmit Request Set reg 1 */#define CAN_TRR1 0xFFC02A0C /* Transmit Request Reset reg 1 */#define CAN_TA1 0xFFC02A10 /* Transmit Acknowledge reg 1 */#define CAN_AA1 0xFFC02A14 /* Transmit Abort Acknowledge reg 1 */#define CAN_RMP1 0xFFC02A18 /* Receive Message Pending reg 1 */#define CAN_RML1 0xFFC02A1C /* Receive Message Lost reg 1 */#define CAN_MBTIF1 0xFFC02A20 /* Mailbox Transmit Interrupt Flag reg 1 */#define CAN_MBRIF1 0xFFC02A24 /* Mailbox Receive Interrupt Flag reg 1 */#define CAN_MBIM1 0xFFC02A28 /* Mailbox Interrupt Mask reg 1 */#define CAN_RFH1 0xFFC02A2C /* Remote Frame Handling reg 1 */#define CAN_OPSS1 0xFFC02A30 /* Overwrite Protection Single Shot Xmit reg 1 *//* For Mailboxes 16-31 */#define CAN_MC2 0xFFC02A40 /* Mailbox config reg 2 */#define CAN_MD2 0xFFC02A44 /* Mailbox direction reg 2 */#define CAN_TRS2 0xFFC02A48 /* Transmit Request Set reg 2 */#define CAN_TRR2 0xFFC02A4C /* Transmit Request Reset reg 2 */#define CAN_TA2 0xFFC02A50 /* Transmit Acknowledge reg 2 */#define CAN_AA2 0xFFC02A54 /* Transmit Abort Acknowledge reg 2 */#define CAN_RMP2 0xFFC02A58 /* Receive Message Pending reg 2 */#define CAN_RML2 0xFFC02A5C /* Receive Message Lost reg 2 */#define CAN_MBTIF2 0xFFC02A60 /* Mailbox Transmit Interrupt Flag reg 2 */#define CAN_MBRIF2 0xFFC02A64 /* Mailbox Receive Interrupt Flag reg 2 */#define CAN_MBIM2 0xFFC02A68 /* Mailbox Interrupt Mask reg 2 */#define CAN_RFH2 0xFFC02A6C /* Remote Frame Handling reg 2 */#define CAN_OPSS2 0xFFC02A70 /* Overwrite Protection Single Shot Xmit reg 2 *//* CAN Configuration, Control, and Status Registers */#define CAN_CLOCK 0xFFC02A80 /* Bit Timing Configuration register 0 */#define CAN_TIMING 0xFFC02A84 /* Bit Timing Configuration register 1 */#define CAN_DEBUG 0xFFC02A88 /* Debug Register */#define CAN_STATUS 0xFFC02A8C /* Global Status Register */#define CAN_CEC 0xFFC02A90 /* Error Counter Register */#define CAN_GIS 0xFFC02A94 /* Global Interrupt Status Register */#define CAN_GIM 0xFFC02A98 /* Global Interrupt Mask Register */#define CAN_GIF 0xFFC02A9C /* Global Interrupt Flag Register */#define CAN_CONTROL 0xFFC02AA0 /* Master Control Register */#define CAN_INTR 0xFFC02AA4 /* Interrupt Pending Register */#define CAN_MBTD 0xFFC02AAC /* Mailbox Temporary Disable Feature */#define CAN_EWR 0xFFC02AB0 /* Programmable Warning Level */#define CAN_ESR 0xFFC02AB4 /* Error Status Register */#define CAN_UCREG 0xFFC02AC0 /* Universal Counter Register/Capture Register */#define CAN_UCCNT 0xFFC02AC4 /* Universal Counter */#define CAN_UCRC 0xFFC02AC8 /* Universal Counter Force Reload Register */#define CAN_UCCNF 0xFFC02ACC /* Universal Counter Configuration Register *//* Mailbox Acceptance Masks */#define CAN_AM00L 0xFFC02B00 /* Mailbox 0 Low Acceptance Mask */#define CAN_AM00H 0xFFC02B04 /* Mailbox 0 High Acceptance Mask */#define CAN_AM01L 0xFFC02B08 /* Mailbox 1 Low Acceptance Mask */#define CAN_AM01H 0xFFC02B0C /* Mailbox 1 High Acceptance Mask */#define CAN_AM02L 0xFFC02B10 /* Mailbox 2 Low Acceptance Mask */#define CAN_AM02H 0xFFC02B14 /* Mailbox 2 High Acceptance Mask */#define CAN_AM03L 0xFFC02B18 /* Mailbox 3 Low Acceptance Mask */#define CAN_AM03H 0xFFC02B1C /* Mailbox 3 High Acceptance Mask */#define CAN_AM04L 0xFFC02B20 /* Mailbox 4 Low Acceptance Mask */#define CAN_AM04H 0xFFC02B24 /* Mailbox 4 High Acceptance Mask */#define CAN_AM05L 0xFFC02B28 /* Mailbox 5 Low Acceptance Mask */#define CAN_AM05H 0xFFC02B2C /* Mailbox 5 High Acceptance Mask */#define CAN_AM06L 0xFFC02B30 /* Mailbox 6 Low Acceptance Mask */#define CAN_AM06H 0xFFC02B34 /* Mailbox 6 High Acceptance Mask */#define CAN_AM07L 0xFFC02B38 /* Mailbox 7 Low Acceptance Mask */#define CAN_AM07H 0xFFC02B3C /* Mailbox 7 High Acceptance Mask */#define CAN_AM08L 0xFFC02B40 /* Mailbox 8 Low Acceptance Mask */#define CAN_AM08H 0xFFC02B44 /* Mailbox 8 High Acceptance Mask */#define CAN_AM09L 0xFFC02B48 /* Mailbox 9 Low Acceptance Mask */#define CAN_AM09H 0xFFC02B4C /* Mailbox 9 High Acceptance Mask */#define CAN_AM10L 0xFFC02B50 /* Mailbox 10 Low Acceptance Mask */#define CAN_AM10H 0xFFC02B54 /* Mailbox 10 High Acceptance Mask */#define CAN_AM11L 0xFFC02B58 /* Mailbox 11 Low Acceptance Mask */#define CAN_AM11H 0xFFC02B5C /* Mailbox 11 High Acceptance Mask */#define CAN_AM12L 0xFFC02B60 /* Mailbox 12 Low Acceptance Mask */#define CAN_AM12H 0xFFC02B64 /* Mailbox 12 High Acceptance Mask */#define CAN_AM13L 0xFFC02B68 /* Mailbox 13 Low Acceptance Mask */#define CAN_AM13H 0xFFC02B6C /* Mailbox 13 High Acceptance Mask */#define CAN_AM14L 0xFFC02B70 /* Mailbox 14 Low Acceptance Mask */#define CAN_AM14H 0xFFC02B74 /* Mailbox 14 High Acceptance Mask */#define CAN_AM15L 0xFFC02B78 /* Mailbox 15 Low Acceptance Mask */⌨️ 快捷键说明
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