def_lpblackfin.h
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/* * File: include/asm-blackfin/mach-common/def_LPBlackfin.h * Based on: * Author: unknown * COPYRIGHT 2005 Analog Devices * Created: ? * Description: * * Modified: * * Bugs: Enter bugs at http://blackfin.uclinux.org/ * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2, or (at your option) * any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; see the file COPYING. * If not, write to the Free Software Foundation, * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *//* LP Blackfin CORE REGISTER BIT & ADDRESS DEFINITIONS FOR ADSP-BF532/33 */#ifndef _DEF_LPBLACKFIN_H#define _DEF_LPBLACKFIN_H#include <asm/mach/anomaly.h>#define MK_BMSK_(x) (1<<x)#ifndef __ASSEMBLY__#include <linux/types.h>#if ANOMALY_05000198# define NOP_PAD_ANOMALY_05000198 "nop;"#else# define NOP_PAD_ANOMALY_05000198#endif#define bfin_read8(addr) ({ \ uint32_t __v; \ __asm__ __volatile__( \ NOP_PAD_ANOMALY_05000198 \ "%0 = b[%1] (z);" \ : "=d" (__v) \ : "a" (addr) \ ); \ __v; })#define bfin_read16(addr) ({ \ uint32_t __v; \ __asm__ __volatile__( \ NOP_PAD_ANOMALY_05000198 \ "%0 = w[%1] (z);" \ : "=d" (__v) \ : "a" (addr) \ ); \ __v; })#define bfin_read32(addr) ({ \ uint32_t __v; \ __asm__ __volatile__( \ NOP_PAD_ANOMALY_05000198 \ "%0 = [%1];" \ : "=d" (__v) \ : "a" (addr) \ ); \ __v; })#define bfin_write8(addr, val) \ __asm__ __volatile__( \ NOP_PAD_ANOMALY_05000198 \ "b[%0] = %1;" \ : \ : "a" (addr), "d" ((uint8_t)(val)) \ : "memory" \ )#define bfin_write16(addr, val) \ __asm__ __volatile__( \ NOP_PAD_ANOMALY_05000198 \ "w[%0] = %1;" \ : \ : "a" (addr), "d" ((uint16_t)(val)) \ : "memory" \ )#define bfin_write32(addr, val) \ __asm__ __volatile__( \ NOP_PAD_ANOMALY_05000198 \ "[%0] = %1;" \ : \ : "a" (addr), "d" (val) \ : "memory" \ )#endif /* __ASSEMBLY__ *//************************************************** * System Register Bits **************************************************//************************************************** * ASTAT register **************************************************//* definitions of ASTAT bit positions*//*Result of last ALU0 or shifter operation is zero*/#define ASTAT_AZ_P 0x00000000/*Result of last ALU0 or shifter operation is negative*/#define ASTAT_AN_P 0x00000001/*Condition Code, used for holding comparison results*/#define ASTAT_CC_P 0x00000005/*Quotient Bit*/#define ASTAT_AQ_P 0x00000006/*Rounding mode, set for biased, clear for unbiased*/#define ASTAT_RND_MOD_P 0x00000008/*Result of last ALU0 operation generated a carry*/#define ASTAT_AC0_P 0x0000000C/*Result of last ALU0 operation generated a carry*/#define ASTAT_AC0_COPY_P 0x00000002/*Result of last ALU1 operation generated a carry*/#define ASTAT_AC1_P 0x0000000D/*Result of last ALU0 or MAC0 operation overflowed, sticky for MAC*/#define ASTAT_AV0_P 0x00000010/*Sticky version of ASTAT_AV0 */#define ASTAT_AV0S_P 0x00000011/*Result of last MAC1 operation overflowed, sticky for MAC*/#define ASTAT_AV1_P 0x00000012/*Sticky version of ASTAT_AV1 */#define ASTAT_AV1S_P 0x00000013/*Result of last ALU0 or MAC0 operation overflowed*/#define ASTAT_V_P 0x00000018/*Result of last ALU0 or MAC0 operation overflowed*/#define ASTAT_V_COPY_P 0x00000003/*Sticky version of ASTAT_V*/#define ASTAT_VS_P 0x00000019/* Masks *//*Result of last ALU0 or shifter operation is zero*/#define ASTAT_AZ MK_BMSK_(ASTAT_AZ_P)/*Result of last ALU0 or shifter operation is negative*/#define ASTAT_AN MK_BMSK_(ASTAT_AN_P)/*Result of last ALU0 operation generated a carry*/#define ASTAT_AC0 MK_BMSK_(ASTAT_AC0_P)/*Result of last ALU0 operation generated a carry*/#define ASTAT_AC0_COPY MK_BMSK_(ASTAT_AC0_COPY_P)/*Result of last ALU0 operation generated a carry*/#define ASTAT_AC1 MK_BMSK_(ASTAT_AC1_P)/*Result of last ALU0 or MAC0 operation overflowed, sticky for MAC*/#define ASTAT_AV0 MK_BMSK_(ASTAT_AV0_P)/*Result of last MAC1 operation overflowed, sticky for MAC*/#define ASTAT_AV1 MK_BMSK_(ASTAT_AV1_P)/*Condition Code, used for holding comparison results*/#define ASTAT_CC MK_BMSK_(ASTAT_CC_P)/*Quotient Bit*/#define ASTAT_AQ MK_BMSK_(ASTAT_AQ_P)/*Rounding mode, set for biased, clear for unbiased*/#define ASTAT_RND_MOD MK_BMSK_(ASTAT_RND_MOD_P)/*Overflow Bit*/#define ASTAT_V MK_BMSK_(ASTAT_V_P)/*Overflow Bit*/#define ASTAT_V_COPY MK_BMSK_(ASTAT_V_COPY_P)/************************************************** * SEQSTAT register **************************************************//* Bit Positions */#define SEQSTAT_EXCAUSE0_P 0x00000000 /* Last exception cause bit 0 */#define SEQSTAT_EXCAUSE1_P 0x00000001 /* Last exception cause bit 1 */#define SEQSTAT_EXCAUSE2_P 0x00000002 /* Last exception cause bit 2 */#define SEQSTAT_EXCAUSE3_P 0x00000003 /* Last exception cause bit 3 */#define SEQSTAT_EXCAUSE4_P 0x00000004 /* Last exception cause bit 4 */#define SEQSTAT_EXCAUSE5_P 0x00000005 /* Last exception cause bit 5 */#define SEQSTAT_IDLE_REQ_P 0x0000000C /* Pending idle mode request, * set by IDLE instruction. */#define SEQSTAT_SFTRESET_P 0x0000000D /* Indicates whether the last * reset was a software reset * (=1) */#define SEQSTAT_HWERRCAUSE0_P 0x0000000E /* Last hw error cause bit 0 */#define SEQSTAT_HWERRCAUSE1_P 0x0000000F /* Last hw error cause bit 1 */#define SEQSTAT_HWERRCAUSE2_P 0x00000010 /* Last hw error cause bit 2 */#define SEQSTAT_HWERRCAUSE3_P 0x00000011 /* Last hw error cause bit 3 */#define SEQSTAT_HWERRCAUSE4_P 0x00000012 /* Last hw error cause bit 4 *//* Masks *//* Exception cause */#define SEQSTAT_EXCAUSE (MK_BMSK_(SEQSTAT_EXCAUSE0_P) | \ MK_BMSK_(SEQSTAT_EXCAUSE1_P) | \ MK_BMSK_(SEQSTAT_EXCAUSE2_P) | \ MK_BMSK_(SEQSTAT_EXCAUSE3_P) | \ MK_BMSK_(SEQSTAT_EXCAUSE4_P) | \ MK_BMSK_(SEQSTAT_EXCAUSE5_P) | \ 0)/* Indicates whether the last reset was a software reset (=1) */#define SEQSTAT_SFTRESET (MK_BMSK_(SEQSTAT_SFTRESET_P))/* Last hw error cause */#define SEQSTAT_HWERRCAUSE (MK_BMSK_(SEQSTAT_HWERRCAUSE0_P) | \ MK_BMSK_(SEQSTAT_HWERRCAUSE1_P) | \ MK_BMSK_(SEQSTAT_HWERRCAUSE2_P) | \ MK_BMSK_(SEQSTAT_HWERRCAUSE3_P) | \ MK_BMSK_(SEQSTAT_HWERRCAUSE4_P) | \ 0)/* Translate bits to something useful *//* Last hw error cause */#define SEQSTAT_HWERRCAUSE_SHIFT (14)#define SEQSTAT_HWERRCAUSE_SYSTEM_MMR (0x02 << SEQSTAT_HWERRCAUSE_SHIFT)#define SEQSTAT_HWERRCAUSE_EXTERN_ADDR (0x03 << SEQSTAT_HWERRCAUSE_SHIFT)#define SEQSTAT_HWERRCAUSE_PERF_FLOW (0x12 << SEQSTAT_HWERRCAUSE_SHIFT)#define SEQSTAT_HWERRCAUSE_RAISE_5 (0x18 << SEQSTAT_HWERRCAUSE_SHIFT)/************************************************** * SYSCFG register **************************************************//* Bit Positions */#define SYSCFG_SSSTEP_P 0x00000000 /* Supervisor single step, when * set it forces an exception * for each instruction executed */#define SYSCFG_CCEN_P 0x00000001 /* Enable cycle counter (=1) */#define SYSCFG_SNEN_P 0x00000002 /* Self nesting Interrupt Enable *//* Masks *//* Supervisor single step, when set it forces an exception for each *instruction executed */#define SYSCFG_SSSTEP MK_BMSK_(SYSCFG_SSSTEP_P )/* Enable cycle counter (=1) */#define SYSCFG_CCEN MK_BMSK_(SYSCFG_CCEN_P )/* Self Nesting Interrupt Enable */#define SYSCFG_SNEN MK_BMSK_(SYSCFG_SNEN_P)/* Backward-compatibility for typos in prior releases */#define SYSCFG_SSSSTEP SYSCFG_SSSTEP#define SYSCFG_CCCEN SYSCFG_CCEN/**************************************************** * Core MMR Register Map ****************************************************//* Data Cache & SRAM Memory (0xFFE00000 - 0xFFE00404) */#define SRAM_BASE_ADDRESS 0xFFE00000 /* SRAM Base Address Register */#define DMEM_CONTROL 0xFFE00004 /* Data memory control */#define DCPLB_STATUS 0xFFE00008 /* Data Cache Programmable Look-Aside * Buffer Status */#define DCPLB_FAULT_STATUS 0xFFE00008 /* "" (older define) */#define DCPLB_FAULT_ADDR 0xFFE0000C /* Data Cache Programmable Look-Aside * Buffer Fault Address */#define DCPLB_ADDR0 0xFFE00100 /* Data Cache Protection Lookaside * Buffer 0 */#define DCPLB_ADDR1 0xFFE00104 /* Data Cache Protection Lookaside * Buffer 1 */#define DCPLB_ADDR2 0xFFE00108 /* Data Cache Protection Lookaside * Buffer 2 */#define DCPLB_ADDR3 0xFFE0010C /* Data Cacheability Protection * Lookaside Buffer 3 */#define DCPLB_ADDR4 0xFFE00110 /* Data Cacheability Protection * Lookaside Buffer 4 */#define DCPLB_ADDR5 0xFFE00114 /* Data Cacheability Protection * Lookaside Buffer 5 */#define DCPLB_ADDR6 0xFFE00118 /* Data Cacheability Protection * Lookaside Buffer 6 */#define DCPLB_ADDR7 0xFFE0011C /* Data Cacheability Protection * Lookaside Buffer 7 */#define DCPLB_ADDR8 0xFFE00120 /* Data Cacheability Protection * Lookaside Buffer 8 */#define DCPLB_ADDR9 0xFFE00124 /* Data Cacheability Protection * Lookaside Buffer 9 */#define DCPLB_ADDR10 0xFFE00128 /* Data Cacheability Protection * Lookaside Buffer 10 */#define DCPLB_ADDR11 0xFFE0012C /* Data Cacheability Protection * Lookaside Buffer 11 */#define DCPLB_ADDR12 0xFFE00130 /* Data Cacheability Protection * Lookaside Buffer 12 */#define DCPLB_ADDR13 0xFFE00134 /* Data Cacheability Protection * Lookaside Buffer 13 */#define DCPLB_ADDR14 0xFFE00138 /* Data Cacheability Protection * Lookaside Buffer 14 */#define DCPLB_ADDR15 0xFFE0013C /* Data Cacheability Protection * Lookaside Buffer 15 */#define DCPLB_DATA0 0xFFE00200 /* Data Cache 0 Status */#define DCPLB_DATA1 0xFFE00204 /* Data Cache 1 Status */#define DCPLB_DATA2 0xFFE00208 /* Data Cache 2 Status */#define DCPLB_DATA3 0xFFE0020C /* Data Cache 3 Status */#define DCPLB_DATA4 0xFFE00210 /* Data Cache 4 Status */#define DCPLB_DATA5 0xFFE00214 /* Data Cache 5 Status */#define DCPLB_DATA6 0xFFE00218 /* Data Cache 6 Status */#define DCPLB_DATA7 0xFFE0021C /* Data Cache 7 Status */#define DCPLB_DATA8 0xFFE00220 /* Data Cache 8 Status */#define DCPLB_DATA9 0xFFE00224 /* Data Cache 9 Status */#define DCPLB_DATA10 0xFFE00228 /* Data Cache 10 Status */#define DCPLB_DATA11 0xFFE0022C /* Data Cache 11 Status */#define DCPLB_DATA12 0xFFE00230 /* Data Cache 12 Status */#define DCPLB_DATA13 0xFFE00234 /* Data Cache 13 Status */#define DCPLB_DATA14 0xFFE00238 /* Data Cache 14 Status */#define DCPLB_DATA15 0xFFE0023C /* Data Cache 15 Status */#define DCPLB_DATA16 0xFFE00240 /* Extra Dummy entry */#define DTEST_COMMAND 0xFFE00300 /* Data Test Command Register */#define DTEST_DATA0 0xFFE00400 /* Data Test Data Register */#define DTEST_DATA1 0xFFE00404 /* Data Test Data Register *//* Instruction Cache & SRAM Memory (0xFFE01004 - 0xFFE01404) */#define IMEM_CONTROL 0xFFE01004 /* Instruction Memory Control */#define ICPLB_STATUS 0xFFE01008 /* Instruction Cache miss status */#define CODE_FAULT_STATUS 0xFFE01008 /* "" (older define) */#define ICPLB_FAULT_ADDR 0xFFE0100C /* Instruction Cache miss address */#define CODE_FAULT_ADDR 0xFFE0100C /* "" (older define) */#define ICPLB_ADDR0 0xFFE01100 /* Instruction Cacheability * Protection Lookaside Buffer 0 */#define ICPLB_ADDR1 0xFFE01104 /* Instruction Cacheability * Protection Lookaside Buffer 1 */#define ICPLB_ADDR2 0xFFE01108 /* Instruction Cacheability * Protection Lookaside Buffer 2 */#define ICPLB_ADDR3 0xFFE0110C /* Instruction Cacheability * Protection Lookaside Buffer 3 */⌨️ 快捷键说明
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