cdefbf52x_base.h
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/* * File: include/asm-blackfin/mach-bf527/cdefBF52x_base.h * Based on: * Author: * * Created: * Description: * * Rev: * * Modified: * * Bugs: Enter bugs at http://blackfin.uclinux.org/ * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2, or (at your option) * any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; see the file COPYING. * If not, write to the Free Software Foundation, * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */#ifndef _CDEF_BF52X_H#include "defBF52x_base.h"/* ==== begin from cdefBF534.h ==== *//* Clock and System Control (0xFFC00000 - 0xFFC000FF) */#define bfin_read_PLL_CTL() bfin_read16(PLL_CTL)#define bfin_write_PLL_CTL(val) bfin_write16(PLL_CTL, val)#define bfin_read_PLL_DIV() bfin_read16(PLL_DIV)#define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV, val)#define bfin_read_VR_CTL() bfin_read16(VR_CTL)#define bfin_write_VR_CTL(val) bfin_write16(VR_CTL, val)#define bfin_read_PLL_STAT() bfin_read16(PLL_STAT)#define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT, val)#define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT)#define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT, val)#define bfin_read_CHIPID() bfin_read32(CHIPID)#define bfin_write_CHIPID(val) bfin_write32(CHIPID, val)/* System Interrupt Controller (0xFFC00100 - 0xFFC001FF) */#define bfin_read_SWRST() bfin_read16(SWRST)#define bfin_write_SWRST(val) bfin_write16(SWRST, val)#define bfin_read_SYSCR() bfin_read16(SYSCR)#define bfin_write_SYSCR(val) bfin_write16(SYSCR, val)#define bfin_read_SIC_RVECT() bfin_read32(SIC_RVECT)#define bfin_write_SIC_RVECT(val) bfin_write32(SIC_RVECT, val)#define bfin_read_SIC_IMASK0() bfin_read32(SIC_IMASK0)#define bfin_write_SIC_IMASK0(val) bfin_write32(SIC_IMASK0, val)#define bfin_read_SIC_IMASK(x) bfin_read32(SIC_IMASK0 + (x << 6))#define bfin_write_SIC_IMASK(x, val) bfin_write32((SIC_IMASK0 + (x << 6)), val)#define bfin_read_SIC_IAR0() bfin_read32(SIC_IAR0)#define bfin_write_SIC_IAR0(val) bfin_write32(SIC_IAR0, val)#define bfin_read_SIC_IAR1() bfin_read32(SIC_IAR1)#define bfin_write_SIC_IAR1(val) bfin_write32(SIC_IAR1, val)#define bfin_read_SIC_IAR2() bfin_read32(SIC_IAR2)#define bfin_write_SIC_IAR2(val) bfin_write32(SIC_IAR2, val)#define bfin_read_SIC_IAR3() bfin_read32(SIC_IAR3)#define bfin_write_SIC_IAR3(val) bfin_write32(SIC_IAR3, val)#define bfin_read_SIC_ISR0() bfin_read32(SIC_ISR0)#define bfin_write_SIC_ISR0(val) bfin_write32(SIC_ISR0, val)#define bfin_read_SIC_ISR(x) bfin_read32(SIC_ISR0 + (x << 6))#define bfin_write_SIC_ISR(x, val) bfin_write32((SIC_ISR0 + (x << 6)), val)#define bfin_read_SIC_IWR0() bfin_read32(SIC_IWR0)#define bfin_write_SIC_IWR0(val) bfin_write32(SIC_IWR0, val)#define bfin_read_SIC_IWR(x) bfin_read32(SIC_IWR0 + (x << 6))#define bfin_write_SIC_IWR(x, val) bfin_write32((SIC_IWR0 + (x << 6)), val)/* SIC Additions to ADSP-BF52x (0xFFC0014C - 0xFFC00162) */#define bfin_read_SIC_IMASK1() bfin_read32(SIC_IMASK1)#define bfin_write_SIC_IMASK1(val) bfin_write32(SIC_IMASK1, val)#define bfin_read_SIC_IAR4() bfin_read32(SIC_IAR4)#define bfin_write_SIC_IAR4(val) bfin_write32(SIC_IAR4, val)#define bfin_read_SIC_IAR5() bfin_read32(SIC_IAR5)#define bfin_write_SIC_IAR5(val) bfin_write32(SIC_IAR5, val)#define bfin_read_SIC_IAR6() bfin_read32(SIC_IAR6)#define bfin_write_SIC_IAR6(val) bfin_write32(SIC_IAR6, val)#define bfin_read_SIC_IAR7() bfin_read32(SIC_IAR7)#define bfin_write_SIC_IAR7(val) bfin_write32(SIC_IAR7, val)#define bfin_read_SIC_ISR1() bfin_read32(SIC_ISR1)#define bfin_write_SIC_ISR1(val) bfin_write32(SIC_ISR1, val)#define bfin_read_SIC_IWR1() bfin_read32(SIC_IWR1)#define bfin_write_SIC_IWR1(val) bfin_write32(SIC_IWR1, val)/* Watchdog Timer (0xFFC00200 - 0xFFC002FF) */#define bfin_read_WDOG_CTL() bfin_read16(WDOG_CTL)#define bfin_write_WDOG_CTL(val) bfin_write16(WDOG_CTL, val)#define bfin_read_WDOG_CNT() bfin_read32(WDOG_CNT)#define bfin_write_WDOG_CNT(val) bfin_write32(WDOG_CNT, val)#define bfin_read_WDOG_STAT() bfin_read32(WDOG_STAT)#define bfin_write_WDOG_STAT(val) bfin_write32(WDOG_STAT, val)/* Real Time Clock (0xFFC00300 - 0xFFC003FF) */#define bfin_read_RTC_STAT() bfin_read32(RTC_STAT)#define bfin_write_RTC_STAT(val) bfin_write32(RTC_STAT, val)#define bfin_read_RTC_ICTL() bfin_read16(RTC_ICTL)#define bfin_write_RTC_ICTL(val) bfin_write16(RTC_ICTL, val)#define bfin_read_RTC_ISTAT() bfin_read16(RTC_ISTAT)#define bfin_write_RTC_ISTAT(val) bfin_write16(RTC_ISTAT, val)#define bfin_read_RTC_SWCNT() bfin_read16(RTC_SWCNT)#define bfin_write_RTC_SWCNT(val) bfin_write16(RTC_SWCNT, val)#define bfin_read_RTC_ALARM() bfin_read32(RTC_ALARM)#define bfin_write_RTC_ALARM(val) bfin_write32(RTC_ALARM, val)#define bfin_read_RTC_FAST() bfin_read16(RTC_FAST)#define bfin_write_RTC_FAST(val) bfin_write16(RTC_FAST, val)#define bfin_read_RTC_PREN() bfin_read16(RTC_PREN)#define bfin_write_RTC_PREN(val) bfin_write16(RTC_PREN, val)/* UART0 Controller (0xFFC00400 - 0xFFC004FF) */#define bfin_read_UART0_THR() bfin_read16(UART0_THR)#define bfin_write_UART0_THR(val) bfin_write16(UART0_THR, val)#define bfin_read_UART0_RBR() bfin_read16(UART0_RBR)#define bfin_write_UART0_RBR(val) bfin_write16(UART0_RBR, val)#define bfin_read_UART0_DLL() bfin_read16(UART0_DLL)#define bfin_write_UART0_DLL(val) bfin_write16(UART0_DLL, val)#define bfin_read_UART0_IER() bfin_read16(UART0_IER)#define bfin_write_UART0_IER(val) bfin_write16(UART0_IER, val)#define bfin_read_UART0_DLH() bfin_read16(UART0_DLH)#define bfin_write_UART0_DLH(val) bfin_write16(UART0_DLH, val)#define bfin_read_UART0_IIR() bfin_read16(UART0_IIR)#define bfin_write_UART0_IIR(val) bfin_write16(UART0_IIR, val)#define bfin_read_UART0_LCR() bfin_read16(UART0_LCR)#define bfin_write_UART0_LCR(val) bfin_write16(UART0_LCR, val)#define bfin_read_UART0_MCR() bfin_read16(UART0_MCR)#define bfin_write_UART0_MCR(val) bfin_write16(UART0_MCR, val)#define bfin_read_UART0_LSR() bfin_read16(UART0_LSR)#define bfin_write_UART0_LSR(val) bfin_write16(UART0_LSR, val)#define bfin_read_UART0_MSR() bfin_read16(UART0_MSR)#define bfin_write_UART0_MSR(val) bfin_write16(UART0_MSR, val)#define bfin_read_UART0_SCR() bfin_read16(UART0_SCR)#define bfin_write_UART0_SCR(val) bfin_write16(UART0_SCR, val)#define bfin_read_UART0_GCTL() bfin_read16(UART0_GCTL)#define bfin_write_UART0_GCTL(val) bfin_write16(UART0_GCTL, val)/* SPI Controller (0xFFC00500 - 0xFFC005FF) */#define bfin_read_SPI_CTL() bfin_read16(SPI_CTL)#define bfin_write_SPI_CTL(val) bfin_write16(SPI_CTL, val)#define bfin_read_SPI_FLG() bfin_read16(SPI_FLG)#define bfin_write_SPI_FLG(val) bfin_write16(SPI_FLG, val)#define bfin_read_SPI_STAT() bfin_read16(SPI_STAT)#define bfin_write_SPI_STAT(val) bfin_write16(SPI_STAT, val)#define bfin_read_SPI_TDBR() bfin_read16(SPI_TDBR)#define bfin_write_SPI_TDBR(val) bfin_write16(SPI_TDBR, val)#define bfin_read_SPI_RDBR() bfin_read16(SPI_RDBR)#define bfin_write_SPI_RDBR(val) bfin_write16(SPI_RDBR, val)#define bfin_read_SPI_BAUD() bfin_read16(SPI_BAUD)#define bfin_write_SPI_BAUD(val) bfin_write16(SPI_BAUD, val)#define bfin_read_SPI_SHADOW() bfin_read16(SPI_SHADOW)#define bfin_write_SPI_SHADOW(val) bfin_write16(SPI_SHADOW, val)/* TIMER0-7 Registers (0xFFC00600 - 0xFFC006FF) */#define bfin_read_TIMER0_CONFIG() bfin_read16(TIMER0_CONFIG)#define bfin_write_TIMER0_CONFIG(val) bfin_write16(TIMER0_CONFIG, val)#define bfin_read_TIMER0_COUNTER() bfin_read32(TIMER0_COUNTER)#define bfin_write_TIMER0_COUNTER(val) bfin_write32(TIMER0_COUNTER, val)#define bfin_read_TIMER0_PERIOD() bfin_read32(TIMER0_PERIOD)#define bfin_write_TIMER0_PERIOD(val) bfin_write32(TIMER0_PERIOD, val)#define bfin_read_TIMER0_WIDTH() bfin_read32(TIMER0_WIDTH)#define bfin_write_TIMER0_WIDTH(val) bfin_write32(TIMER0_WIDTH, val)#define bfin_read_TIMER1_CONFIG() bfin_read16(TIMER1_CONFIG)#define bfin_write_TIMER1_CONFIG(val) bfin_write16(TIMER1_CONFIG, val)#define bfin_read_TIMER1_COUNTER() bfin_read32(TIMER1_COUNTER)#define bfin_write_TIMER1_COUNTER(val) bfin_write32(TIMER1_COUNTER, val)#define bfin_read_TIMER1_PERIOD() bfin_read32(TIMER1_PERIOD)#define bfin_write_TIMER1_PERIOD(val) bfin_write32(TIMER1_PERIOD, val)#define bfin_read_TIMER1_WIDTH() bfin_read32(TIMER1_WIDTH)#define bfin_write_TIMER1_WIDTH(val) bfin_write32(TIMER1_WIDTH, val)#define bfin_read_TIMER2_CONFIG() bfin_read16(TIMER2_CONFIG)#define bfin_write_TIMER2_CONFIG(val) bfin_write16(TIMER2_CONFIG, val)#define bfin_read_TIMER2_COUNTER() bfin_read32(TIMER2_COUNTER)#define bfin_write_TIMER2_COUNTER(val) bfin_write32(TIMER2_COUNTER, val)#define bfin_read_TIMER2_PERIOD() bfin_read32(TIMER2_PERIOD)#define bfin_write_TIMER2_PERIOD(val) bfin_write32(TIMER2_PERIOD, val)#define bfin_read_TIMER2_WIDTH() bfin_read32(TIMER2_WIDTH)#define bfin_write_TIMER2_WIDTH(val) bfin_write32(TIMER2_WIDTH, val)#define bfin_read_TIMER3_CONFIG() bfin_read16(TIMER3_CONFIG)#define bfin_write_TIMER3_CONFIG(val) bfin_write16(TIMER3_CONFIG, val)#define bfin_read_TIMER3_COUNTER() bfin_read32(TIMER3_COUNTER)#define bfin_write_TIMER3_COUNTER(val) bfin_write32(TIMER3_COUNTER, val)#define bfin_read_TIMER3_PERIOD() bfin_read32(TIMER3_PERIOD)#define bfin_write_TIMER3_PERIOD(val) bfin_write32(TIMER3_PERIOD, val)#define bfin_read_TIMER3_WIDTH() bfin_read32(TIMER3_WIDTH)#define bfin_write_TIMER3_WIDTH(val) bfin_write32(TIMER3_WIDTH, val)#define bfin_read_TIMER4_CONFIG() bfin_read16(TIMER4_CONFIG)#define bfin_write_TIMER4_CONFIG(val) bfin_write16(TIMER4_CONFIG, val)#define bfin_read_TIMER4_COUNTER() bfin_read32(TIMER4_COUNTER)#define bfin_write_TIMER4_COUNTER(val) bfin_write32(TIMER4_COUNTER, val)⌨️ 快捷键说明
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