defbf525.h
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/* USB Channel 2 Config Registers */#define USB_DMA2CONTROL 0xffc03c44 /* DMA master channel 2 configuration */#define USB_DMA2ADDRLOW 0xffc03c48 /* Lower 16-bits of memory source/destination address for DMA master channel 2 */#define USB_DMA2ADDRHIGH 0xffc03c4c /* Upper 16-bits of memory source/destination address for DMA master channel 2 */#define USB_DMA2COUNTLOW 0xffc03c50 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 2 */#define USB_DMA2COUNTHIGH 0xffc03c54 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 2 *//* USB Channel 3 Config Registers */#define USB_DMA3CONTROL 0xffc03c64 /* DMA master channel 3 configuration */#define USB_DMA3ADDRLOW 0xffc03c68 /* Lower 16-bits of memory source/destination address for DMA master channel 3 */#define USB_DMA3ADDRHIGH 0xffc03c6c /* Upper 16-bits of memory source/destination address for DMA master channel 3 */#define USB_DMA3COUNTLOW 0xffc03c70 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 3 */#define USB_DMA3COUNTHIGH 0xffc03c74 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 3 *//* USB Channel 4 Config Registers */#define USB_DMA4CONTROL 0xffc03c84 /* DMA master channel 4 configuration */#define USB_DMA4ADDRLOW 0xffc03c88 /* Lower 16-bits of memory source/destination address for DMA master channel 4 */#define USB_DMA4ADDRHIGH 0xffc03c8c /* Upper 16-bits of memory source/destination address for DMA master channel 4 */#define USB_DMA4COUNTLOW 0xffc03c90 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 4 */#define USB_DMA4COUNTHIGH 0xffc03c94 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 4 *//* USB Channel 5 Config Registers */#define USB_DMA5CONTROL 0xffc03ca4 /* DMA master channel 5 configuration */#define USB_DMA5ADDRLOW 0xffc03ca8 /* Lower 16-bits of memory source/destination address for DMA master channel 5 */#define USB_DMA5ADDRHIGH 0xffc03cac /* Upper 16-bits of memory source/destination address for DMA master channel 5 */#define USB_DMA5COUNTLOW 0xffc03cb0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 5 */#define USB_DMA5COUNTHIGH 0xffc03cb4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 5 *//* USB Channel 6 Config Registers */#define USB_DMA6CONTROL 0xffc03cc4 /* DMA master channel 6 configuration */#define USB_DMA6ADDRLOW 0xffc03cc8 /* Lower 16-bits of memory source/destination address for DMA master channel 6 */#define USB_DMA6ADDRHIGH 0xffc03ccc /* Upper 16-bits of memory source/destination address for DMA master channel 6 */#define USB_DMA6COUNTLOW 0xffc03cd0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 6 */#define USB_DMA6COUNTHIGH 0xffc03cd4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 6 *//* USB Channel 7 Config Registers */#define USB_DMA7CONTROL 0xffc03ce4 /* DMA master channel 7 configuration */#define USB_DMA7ADDRLOW 0xffc03ce8 /* Lower 16-bits of memory source/destination address for DMA master channel 7 */#define USB_DMA7ADDRHIGH 0xffc03cec /* Upper 16-bits of memory source/destination address for DMA master channel 7 */#define USB_DMA7COUNTLOW 0xffc03cf0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */#define USB_DMA7COUNTHIGH 0xffc03cf4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 *//* Bit masks for USB_FADDR */#define FUNCTION_ADDRESS 0x7f /* Function address *//* Bit masks for USB_POWER */#define ENABLE_SUSPENDM 0x1 /* enable SuspendM output */#define nENABLE_SUSPENDM 0x0 #define SUSPEND_MODE 0x2 /* Suspend Mode indicator */#define nSUSPEND_MODE 0x0 #define RESUME_MODE 0x4 /* DMA Mode */#define nRESUME_MODE 0x0 #define RESET 0x8 /* Reset indicator */#define nRESET 0x0 #define HS_MODE 0x10 /* High Speed mode indicator */#define nHS_MODE 0x0 #define HS_ENABLE 0x20 /* high Speed Enable */#define nHS_ENABLE 0x0 #define SOFT_CONN 0x40 /* Soft connect */#define nSOFT_CONN 0x0 #define ISO_UPDATE 0x80 /* Isochronous update */#define nISO_UPDATE 0x0 /* Bit masks for USB_INTRTX */#define EP0_TX 0x1 /* Tx Endpoint 0 interrupt */#define nEP0_TX 0x0 #define EP1_TX 0x2 /* Tx Endpoint 1 interrupt */#define nEP1_TX 0x0 #define EP2_TX 0x4 /* Tx Endpoint 2 interrupt */#define nEP2_TX 0x0 #define EP3_TX 0x8 /* Tx Endpoint 3 interrupt */#define nEP3_TX 0x0 #define EP4_TX 0x10 /* Tx Endpoint 4 interrupt */#define nEP4_TX 0x0 #define EP5_TX 0x20 /* Tx Endpoint 5 interrupt */#define nEP5_TX 0x0 #define EP6_TX 0x40 /* Tx Endpoint 6 interrupt */#define nEP6_TX 0x0 #define EP7_TX 0x80 /* Tx Endpoint 7 interrupt */#define nEP7_TX 0x0 /* Bit masks for USB_INTRRX */#define EP1_RX 0x2 /* Rx Endpoint 1 interrupt */#define nEP1_RX 0x0 #define EP2_RX 0x4 /* Rx Endpoint 2 interrupt */#define nEP2_RX 0x0 #define EP3_RX 0x8 /* Rx Endpoint 3 interrupt */#define nEP3_RX 0x0 #define EP4_RX 0x10 /* Rx Endpoint 4 interrupt */#define nEP4_RX 0x0 #define EP5_RX 0x20 /* Rx Endpoint 5 interrupt */#define nEP5_RX 0x0 #define EP6_RX 0x40 /* Rx Endpoint 6 interrupt */#define nEP6_RX 0x0 #define EP7_RX 0x80 /* Rx Endpoint 7 interrupt */#define nEP7_RX 0x0 /* Bit masks for USB_INTRTXE */#define EP0_TX_E 0x1 /* Endpoint 0 interrupt Enable */#define nEP0_TX_E 0x0 #define EP1_TX_E 0x2 /* Tx Endpoint 1 interrupt Enable */#define nEP1_TX_E 0x0 #define EP2_TX_E 0x4 /* Tx Endpoint 2 interrupt Enable */#define nEP2_TX_E 0x0 #define EP3_TX_E 0x8 /* Tx Endpoint 3 interrupt Enable */#define nEP3_TX_E 0x0 #define EP4_TX_E 0x10 /* Tx Endpoint 4 interrupt Enable */#define nEP4_TX_E 0x0 #define EP5_TX_E 0x20 /* Tx Endpoint 5 interrupt Enable */#define nEP5_TX_E 0x0 #define EP6_TX_E 0x40 /* Tx Endpoint 6 interrupt Enable */#define nEP6_TX_E 0x0 #define EP7_TX_E 0x80 /* Tx Endpoint 7 interrupt Enable */#define nEP7_TX_E 0x0 /* Bit masks for USB_INTRRXE */#define EP1_RX_E 0x2 /* Rx Endpoint 1 interrupt Enable */#define nEP1_RX_E 0x0 #define EP2_RX_E 0x4 /* Rx Endpoint 2 interrupt Enable */#define nEP2_RX_E 0x0 #define EP3_RX_E 0x8 /* Rx Endpoint 3 interrupt Enable */#define nEP3_RX_E 0x0 #define EP4_RX_E 0x10 /* Rx Endpoint 4 interrupt Enable */#define nEP4_RX_E 0x0 #define EP5_RX_E 0x20 /* Rx Endpoint 5 interrupt Enable */#define nEP5_RX_E 0x0 #define EP6_RX_E 0x40 /* Rx Endpoint 6 interrupt Enable */#define nEP6_RX_E 0x0 #define EP7_RX_E 0x80 /* Rx Endpoint 7 interrupt Enable */#define nEP7_RX_E 0x0 /* Bit masks for USB_INTRUSB */#define SUSPEND_B 0x1 /* Suspend indicator */#define nSUSPEND_B 0x0 #define RESUME_B 0x2 /* Resume indicator */#define nRESUME_B 0x0 #define RESET_OR_BABLE_B 0x4 /* Reset/babble indicator */#define nRESET_OR_BABLE_B 0x0 #define SOF_B 0x8 /* Start of frame */#define nSOF_B 0x0 #define CONN_B 0x10 /* Connection indicator */#define nCONN_B 0x0 #define DISCON_B 0x20 /* Disconnect indicator */#define nDISCON_B 0x0 #define SESSION_REQ_B 0x40 /* Session Request */#define nSESSION_REQ_B 0x0 #define VBUS_ERROR_B 0x80 /* Vbus threshold indicator */#define nVBUS_ERROR_B 0x0 /* Bit masks for USB_INTRUSBE */#define SUSPEND_BE 0x1 /* Suspend indicator int enable */#define nSUSPEND_BE 0x0 #define RESUME_BE 0x2 /* Resume indicator int enable */#define nRESUME_BE 0x0 #define RESET_OR_BABLE_BE 0x4 /* Reset/babble indicator int enable */#define nRESET_OR_BABLE_BE 0x0 #define SOF_BE 0x8 /* Start of frame int enable */#define nSOF_BE 0x0 #define CONN_BE 0x10 /* Connection indicator int enable */#define nCONN_BE 0x0 #define DISCON_BE 0x20 /* Disconnect indicator int enable */#define nDISCON_BE 0x0 #define SESSION_REQ_BE 0x40 /* Session Request int enable */#define nSESSION_REQ_BE 0x0 #define VBUS_ERROR_BE 0x80 /* Vbus threshold indicator int enable */#define nVBUS_ERROR_BE 0x0 /* Bit masks for USB_FRAME */#define FRAME_NUMBER 0x7ff /* Frame number *//* Bit masks for USB_INDEX */#define SELECTED_ENDPOINT 0xf /* selected endpoint *//* Bit masks for USB_GLOBAL_CTL */#define GLOBAL_ENA 0x1 /* enables USB module */#define nGLOBAL_ENA 0x0 #define EP1_TX_ENA 0x2 /* Transmit endpoint 1 enable */#define nEP1_TX_ENA 0x0 #define EP2_TX_ENA 0x4 /* Transmit endpoint 2 enable */#define nEP2_TX_ENA 0x0 #define EP3_TX_ENA 0x8 /* Transmit endpoint 3 enable */#define nEP3_TX_ENA 0x0 #define EP4_TX_ENA 0x10 /* Transmit endpoint 4 enable */#define nEP4_TX_ENA 0x0 #define EP5_TX_ENA 0x20 /* Transmit endpoint 5 enable */#define nEP5_TX_ENA 0x0 #define EP6_TX_ENA 0x40 /* Transmit endpoint 6 enable */#define nEP6_TX_ENA 0x0 #define EP7_TX_ENA 0x80 /* Transmit endpoint 7 enable */#define nEP7_TX_ENA 0x0 #define EP1_RX_ENA 0x100 /* Receive endpoint 1 enable */#define nEP1_RX_ENA 0x0 #define EP2_RX_ENA 0x200 /* Receive endpoint 2 enable */#define nEP2_RX_ENA 0x0 #define EP3_RX_ENA 0x400 /* Receive endpoint 3 enable */#define nEP3_RX_ENA 0x0 #define EP4_RX_ENA 0x800 /* Receive endpoint 4 enable */#define nEP4_RX_ENA 0x0 #define EP5_RX_ENA 0x1000 /* Receive endpoint 5 enable */#define nEP5_RX_ENA 0x0 #define EP6_RX_ENA 0x2000 /* Receive endpoint 6 enable */#define nEP6_RX_ENA 0x0 #define EP7_RX_ENA 0x4000 /* Receive endpoint 7 enable */#define nEP7_RX_ENA 0x0 /* Bit masks for USB_OTG_DEV_CTL */#define SESSION 0x1 /* session indicator */#define nSESSION 0x0 #define HOST_REQ 0x2 /* Host negotiation request */#define nHOST_REQ 0x0 #define HOST_MODE 0x4 /* indicates USBDRC is a host */#define nHOST_MODE 0x0 #define VBUS0 0x8 /* Vbus level indicator[0] */#define nVBUS0 0x0 #define VBUS1 0x10 /* Vbus level indicator[1] */#define nVBUS1 0x0 #define LSDEV 0x20 /* Low-speed indicator */#define nLSDEV 0x0 #define FSDEV 0x40 /* Full or High-speed indicator */⌨️ 快捷键说明
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