cdefbf54x_base.h

来自「linux 内核源代码」· C头文件 代码 · 共 1,112 行 · 第 1/5 页

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#define bfin_read_DMA0_PERIPHERAL_MAP()		bfin_read16(DMA0_PERIPHERAL_MAP)#define bfin_write_DMA0_PERIPHERAL_MAP(val)	bfin_write16(DMA0_PERIPHERAL_MAP, val)#define bfin_read_DMA0_CURR_X_COUNT()		bfin_read16(DMA0_CURR_X_COUNT)#define bfin_write_DMA0_CURR_X_COUNT(val)	bfin_write16(DMA0_CURR_X_COUNT, val)#define bfin_read_DMA0_CURR_Y_COUNT()		bfin_read16(DMA0_CURR_Y_COUNT)#define bfin_write_DMA0_CURR_Y_COUNT(val)	bfin_write16(DMA0_CURR_Y_COUNT, val)/* DMA Channel 1 Registers */#define bfin_read_DMA1_NEXT_DESC_PTR() 		bfin_read32(DMA1_NEXT_DESC_PTR)#define bfin_write_DMA1_NEXT_DESC_PTR(val) 	bfin_write32(DMA1_NEXT_DESC_PTR)#define bfin_read_DMA1_START_ADDR() 		bfin_read32(DMA1_START_ADDR)#define bfin_write_DMA1_START_ADDR(val) 	bfin_write32(DMA1_START_ADDR)#define bfin_read_DMA1_CONFIG()			bfin_read16(DMA1_CONFIG)#define bfin_write_DMA1_CONFIG(val)		bfin_write16(DMA1_CONFIG, val)#define bfin_read_DMA1_X_COUNT()		bfin_read16(DMA1_X_COUNT)#define bfin_write_DMA1_X_COUNT(val)		bfin_write16(DMA1_X_COUNT, val)#define bfin_read_DMA1_X_MODIFY()		bfin_read16(DMA1_X_MODIFY)#define bfin_write_DMA1_X_MODIFY(val) 		bfin_write16(DMA1_X_MODIFY)#define bfin_read_DMA1_Y_COUNT()		bfin_read16(DMA1_Y_COUNT)#define bfin_write_DMA1_Y_COUNT(val)		bfin_write16(DMA1_Y_COUNT, val)#define bfin_read_DMA1_Y_MODIFY()		bfin_read16(DMA1_Y_MODIFY)#define bfin_write_DMA1_Y_MODIFY(val) 		bfin_write16(DMA1_Y_MODIFY)#define bfin_read_DMA1_CURR_DESC_PTR() 		bfin_read32(DMA1_CURR_DESC_PTR)#define bfin_write_DMA1_CURR_DESC_PTR(val) 	bfin_write32(DMA1_CURR_DESC_PTR)#define bfin_read_DMA1_CURR_ADDR() 		bfin_read32(DMA1_CURR_ADDR)#define bfin_write_DMA1_CURR_ADDR(val) 		bfin_write32(DMA1_CURR_ADDR)#define bfin_read_DMA1_IRQ_STATUS()		bfin_read16(DMA1_IRQ_STATUS)#define bfin_write_DMA1_IRQ_STATUS(val)		bfin_write16(DMA1_IRQ_STATUS, val)#define bfin_read_DMA1_PERIPHERAL_MAP()		bfin_read16(DMA1_PERIPHERAL_MAP)#define bfin_write_DMA1_PERIPHERAL_MAP(val)	bfin_write16(DMA1_PERIPHERAL_MAP, val)#define bfin_read_DMA1_CURR_X_COUNT()		bfin_read16(DMA1_CURR_X_COUNT)#define bfin_write_DMA1_CURR_X_COUNT(val)	bfin_write16(DMA1_CURR_X_COUNT, val)#define bfin_read_DMA1_CURR_Y_COUNT()		bfin_read16(DMA1_CURR_Y_COUNT)#define bfin_write_DMA1_CURR_Y_COUNT(val)	bfin_write16(DMA1_CURR_Y_COUNT, val)/* DMA Channel 2 Registers */#define bfin_read_DMA2_NEXT_DESC_PTR() 		bfin_read32(DMA2_NEXT_DESC_PTR)#define bfin_write_DMA2_NEXT_DESC_PTR(val) 	bfin_write32(DMA2_NEXT_DESC_PTR)#define bfin_read_DMA2_START_ADDR() 		bfin_read32(DMA2_START_ADDR)#define bfin_write_DMA2_START_ADDR(val) 	bfin_write32(DMA2_START_ADDR)#define bfin_read_DMA2_CONFIG()			bfin_read16(DMA2_CONFIG)#define bfin_write_DMA2_CONFIG(val)		bfin_write16(DMA2_CONFIG, val)#define bfin_read_DMA2_X_COUNT()		bfin_read16(DMA2_X_COUNT)#define bfin_write_DMA2_X_COUNT(val)		bfin_write16(DMA2_X_COUNT, val)#define bfin_read_DMA2_X_MODIFY()		bfin_read16(DMA2_X_MODIFY)#define bfin_write_DMA2_X_MODIFY(val) 		bfin_write16(DMA2_X_MODIFY)#define bfin_read_DMA2_Y_COUNT()		bfin_read16(DMA2_Y_COUNT)#define bfin_write_DMA2_Y_COUNT(val)		bfin_write16(DMA2_Y_COUNT, val)#define bfin_read_DMA2_Y_MODIFY()		bfin_read16(DMA2_Y_MODIFY)#define bfin_write_DMA2_Y_MODIFY(val) 		bfin_write16(DMA2_Y_MODIFY)#define bfin_read_DMA2_CURR_DESC_PTR() 		bfin_read32(DMA2_CURR_DESC_PTR)#define bfin_write_DMA2_CURR_DESC_PTR(val) 	bfin_write32(DMA2_CURR_DESC_PTR)#define bfin_read_DMA2_CURR_ADDR() 		bfin_read32(DMA2_CURR_ADDR)#define bfin_write_DMA2_CURR_ADDR(val) 		bfin_write32(DMA2_CURR_ADDR)#define bfin_read_DMA2_IRQ_STATUS()		bfin_read16(DMA2_IRQ_STATUS)#define bfin_write_DMA2_IRQ_STATUS(val)		bfin_write16(DMA2_IRQ_STATUS, val)#define bfin_read_DMA2_PERIPHERAL_MAP()		bfin_read16(DMA2_PERIPHERAL_MAP)#define bfin_write_DMA2_PERIPHERAL_MAP(val)	bfin_write16(DMA2_PERIPHERAL_MAP, val)#define bfin_read_DMA2_CURR_X_COUNT()		bfin_read16(DMA2_CURR_X_COUNT)#define bfin_write_DMA2_CURR_X_COUNT(val)	bfin_write16(DMA2_CURR_X_COUNT, val)#define bfin_read_DMA2_CURR_Y_COUNT()		bfin_read16(DMA2_CURR_Y_COUNT)#define bfin_write_DMA2_CURR_Y_COUNT(val)	bfin_write16(DMA2_CURR_Y_COUNT, val)/* DMA Channel 3 Registers */#define bfin_read_DMA3_NEXT_DESC_PTR() 		bfin_read32(DMA3_NEXT_DESC_PTR)#define bfin_write_DMA3_NEXT_DESC_PTR(val) 	bfin_write32(DMA3_NEXT_DESC_PTR)#define bfin_read_DMA3_START_ADDR() 		bfin_read32(DMA3_START_ADDR)#define bfin_write_DMA3_START_ADDR(val) 	bfin_write32(DMA3_START_ADDR)#define bfin_read_DMA3_CONFIG()			bfin_read16(DMA3_CONFIG)#define bfin_write_DMA3_CONFIG(val)		bfin_write16(DMA3_CONFIG, val)#define bfin_read_DMA3_X_COUNT()		bfin_read16(DMA3_X_COUNT)#define bfin_write_DMA3_X_COUNT(val)		bfin_write16(DMA3_X_COUNT, val)#define bfin_read_DMA3_X_MODIFY()		bfin_read16(DMA3_X_MODIFY)#define bfin_write_DMA3_X_MODIFY(val) 		bfin_write16(DMA3_X_MODIFY)#define bfin_read_DMA3_Y_COUNT()		bfin_read16(DMA3_Y_COUNT)#define bfin_write_DMA3_Y_COUNT(val)		bfin_write16(DMA3_Y_COUNT, val)#define bfin_read_DMA3_Y_MODIFY()		bfin_read16(DMA3_Y_MODIFY)#define bfin_write_DMA3_Y_MODIFY(val) 		bfin_write16(DMA3_Y_MODIFY)#define bfin_read_DMA3_CURR_DESC_PTR() 		bfin_read32(DMA3_CURR_DESC_PTR)#define bfin_write_DMA3_CURR_DESC_PTR(val) 	bfin_write32(DMA3_CURR_DESC_PTR)#define bfin_read_DMA3_CURR_ADDR() 		bfin_read32(DMA3_CURR_ADDR)#define bfin_write_DMA3_CURR_ADDR(val) 		bfin_write32(DMA3_CURR_ADDR)#define bfin_read_DMA3_IRQ_STATUS()		bfin_read16(DMA3_IRQ_STATUS)#define bfin_write_DMA3_IRQ_STATUS(val)		bfin_write16(DMA3_IRQ_STATUS, val)#define bfin_read_DMA3_PERIPHERAL_MAP()		bfin_read16(DMA3_PERIPHERAL_MAP)#define bfin_write_DMA3_PERIPHERAL_MAP(val)	bfin_write16(DMA3_PERIPHERAL_MAP, val)#define bfin_read_DMA3_CURR_X_COUNT()		bfin_read16(DMA3_CURR_X_COUNT)#define bfin_write_DMA3_CURR_X_COUNT(val)	bfin_write16(DMA3_CURR_X_COUNT, val)#define bfin_read_DMA3_CURR_Y_COUNT()		bfin_read16(DMA3_CURR_Y_COUNT)#define bfin_write_DMA3_CURR_Y_COUNT(val)	bfin_write16(DMA3_CURR_Y_COUNT, val)/* DMA Channel 4 Registers */#define bfin_read_DMA4_NEXT_DESC_PTR() 		bfin_read32(DMA4_NEXT_DESC_PTR)#define bfin_write_DMA4_NEXT_DESC_PTR(val) 	bfin_write32(DMA4_NEXT_DESC_PTR)#define bfin_read_DMA4_START_ADDR() 		bfin_read32(DMA4_START_ADDR)#define bfin_write_DMA4_START_ADDR(val) 	bfin_write32(DMA4_START_ADDR)#define bfin_read_DMA4_CONFIG()			bfin_read16(DMA4_CONFIG)#define bfin_write_DMA4_CONFIG(val)		bfin_write16(DMA4_CONFIG, val)#define bfin_read_DMA4_X_COUNT()		bfin_read16(DMA4_X_COUNT)#define bfin_write_DMA4_X_COUNT(val)		bfin_write16(DMA4_X_COUNT, val)#define bfin_read_DMA4_X_MODIFY()		bfin_read16(DMA4_X_MODIFY)#define bfin_write_DMA4_X_MODIFY(val) 		bfin_write16(DMA4_X_MODIFY)#define bfin_read_DMA4_Y_COUNT()		bfin_read16(DMA4_Y_COUNT)#define bfin_write_DMA4_Y_COUNT(val)		bfin_write16(DMA4_Y_COUNT, val)#define bfin_read_DMA4_Y_MODIFY()		bfin_read16(DMA4_Y_MODIFY)#define bfin_write_DMA4_Y_MODIFY(val) 		bfin_write16(DMA4_Y_MODIFY)#define bfin_read_DMA4_CURR_DESC_PTR() 		bfin_read32(DMA4_CURR_DESC_PTR)#define bfin_write_DMA4_CURR_DESC_PTR(val) 	bfin_write32(DMA4_CURR_DESC_PTR)#define bfin_read_DMA4_CURR_ADDR() 		bfin_read32(DMA4_CURR_ADDR)#define bfin_write_DMA4_CURR_ADDR(val) 		bfin_write32(DMA4_CURR_ADDR)#define bfin_read_DMA4_IRQ_STATUS()		bfin_read16(DMA4_IRQ_STATUS)#define bfin_write_DMA4_IRQ_STATUS(val)		bfin_write16(DMA4_IRQ_STATUS, val)#define bfin_read_DMA4_PERIPHERAL_MAP()		bfin_read16(DMA4_PERIPHERAL_MAP)#define bfin_write_DMA4_PERIPHERAL_MAP(val)	bfin_write16(DMA4_PERIPHERAL_MAP, val)#define bfin_read_DMA4_CURR_X_COUNT()		bfin_read16(DMA4_CURR_X_COUNT)#define bfin_write_DMA4_CURR_X_COUNT(val)	bfin_write16(DMA4_CURR_X_COUNT, val)#define bfin_read_DMA4_CURR_Y_COUNT()		bfin_read16(DMA4_CURR_Y_COUNT)#define bfin_write_DMA4_CURR_Y_COUNT(val)	bfin_write16(DMA4_CURR_Y_COUNT, val)/* DMA Channel 5 Registers */#define bfin_read_DMA5_NEXT_DESC_PTR() 		bfin_read32(DMA5_NEXT_DESC_PTR)#define bfin_write_DMA5_NEXT_DESC_PTR(val) 	bfin_write32(DMA5_NEXT_DESC_PTR)#define bfin_read_DMA5_START_ADDR() 		bfin_read32(DMA5_START_ADDR)#define bfin_write_DMA5_START_ADDR(val) 	bfin_write32(DMA5_START_ADDR)#define bfin_read_DMA5_CONFIG()			bfin_read16(DMA5_CONFIG)#define bfin_write_DMA5_CONFIG(val)		bfin_write16(DMA5_CONFIG, val)#define bfin_read_DMA5_X_COUNT()		bfin_read16(DMA5_X_COUNT)#define bfin_write_DMA5_X_COUNT(val)		bfin_write16(DMA5_X_COUNT, val)#define bfin_read_DMA5_X_MODIFY()		bfin_read16(DMA5_X_MODIFY)#define bfin_write_DMA5_X_MODIFY(val) 		bfin_write16(DMA5_X_MODIFY)#define bfin_read_DMA5_Y_COUNT()		bfin_read16(DMA5_Y_COUNT)#define bfin_write_DMA5_Y_COUNT(val)		bfin_write16(DMA5_Y_COUNT, val)#define bfin_read_DMA5_Y_MODIFY()		bfin_read16(DMA5_Y_MODIFY)#define bfin_write_DMA5_Y_MODIFY(val) 		bfin_write16(DMA5_Y_MODIFY)#define bfin_read_DMA5_CURR_DESC_PTR() 		bfin_read32(DMA5_CURR_DESC_PTR)#define bfin_write_DMA5_CURR_DESC_PTR(val) 	bfin_write32(DMA5_CURR_DESC_PTR)#define bfin_read_DMA5_CURR_ADDR() 		bfin_read32(DMA5_CURR_ADDR)#define bfin_write_DMA5_CURR_ADDR(val) 		bfin_write32(DMA5_CURR_ADDR)#define bfin_read_DMA5_IRQ_STATUS()		bfin_read16(DMA5_IRQ_STATUS)#define bfin_write_DMA5_IRQ_STATUS(val)		bfin_write16(DMA5_IRQ_STATUS, val)#define bfin_read_DMA5_PERIPHERAL_MAP()		bfin_read16(DMA5_PERIPHERAL_MAP)#define bfin_write_DMA5_PERIPHERAL_MAP(val)	bfin_write16(DMA5_PERIPHERAL_MAP, val)#define bfin_read_DMA5_CURR_X_COUNT()		bfin_read16(DMA5_CURR_X_COUNT)#define bfin_write_DMA5_CURR_X_COUNT(val)	bfin_write16(DMA5_CURR_X_COUNT, val)#define bfin_read_DMA5_CURR_Y_COUNT()		bfin_read16(DMA5_CURR_Y_COUNT)#define bfin_write_DMA5_CURR_Y_COUNT(val)	bfin_write16(DMA5_CURR_Y_COUNT, val)/* DMA Channel 6 Registers */#define bfin_read_DMA6_NEXT_DESC_PTR() 		bfin_read32(DMA6_NEXT_DESC_PTR)#define bfin_write_DMA6_NEXT_DESC_PTR(val) 	bfin_write32(DMA6_NEXT_DESC_PTR)#define bfin_read_DMA6_START_ADDR() 		bfin_read32(DMA6_START_ADDR)#define bfin_write_DMA6_START_ADDR(val) 	bfin_write32(DMA6_START_ADDR)#define bfin_read_DMA6_CONFIG()			bfin_read16(DMA6_CONFIG)#define bfin_write_DMA6_CONFIG(val)		bfin_write16(DMA6_CONFIG, val)#define bfin_read_DMA6_X_COUNT()		bfin_read16(DMA6_X_COUNT)#define bfin_write_DMA6_X_COUNT(val)		bfin_write16(DMA6_X_COUNT, val)#define bfin_read_DMA6_X_MODIFY()		bfin_read16(DMA6_X_MODIFY)#define bfin_write_DMA6_X_MODIFY(val) 		bfin_write16(DMA6_X_MODIFY)#define bfin_read_DMA6_Y_COUNT()		bfin_read16(DMA6_Y_COUNT)#define bfin_write_DMA6_Y_COUNT(val)		bfin_write16(DMA6_Y_COUNT, val)#define bfin_read_DMA6_Y_MODIFY()		bfin_read16(DMA6_Y_MODIFY)#define bfin_write_DMA6_Y_MODIFY(val) 		bfin_write16(DMA6_Y_MODIFY)#define bfin_read_DMA6_CURR_DESC_PTR() 		bfin_read32(DMA6_CURR_DESC_PTR)#define bfin_write_DMA6_CURR_DESC_PTR(val) 	bfin_write32(DMA6_CURR_DESC_PTR)#define bfin_read_DMA6_CURR_ADDR() 		bfin_read32(DMA6_CURR_ADDR)#define bfin_write_DMA6_CURR_ADDR(val) 		bfin_write32(DMA6_CURR_ADDR)#define bfin_read_DMA6_IRQ_STATUS()		bfin_read16(DMA6_IRQ_STATUS)#define bfin_write_DMA6_IRQ_STATUS(val)		bfin_write16(DMA6_IRQ_STATUS, val)#define bfin_read_DMA6_PERIPHERAL_MAP()		bfin_read16(DMA6_PERIPHERAL_MAP)#define bfin_write_DMA6_PERIPHERAL_MAP(val)	bfin_write16(DMA6_PERIPHERAL_MAP, val)#define bfin_read_DMA6_CURR_X_COUNT()		bfin_read16(DMA6_CURR_X_COUNT)#define bfin_write_DMA6_CURR_X_COUNT(val)	bfin_write16(DMA6_CURR_X_COUNT, val)#define bfin_read_DMA6_CURR_Y_COUNT()		bfin_read16(DMA6_CURR_Y_COUNT)#define bfin_write_DMA6_CURR_Y_COUNT(val)	bfin_write16(DMA6_CURR_Y_COUNT, val)/* DMA Channel 7 Registers */#define bfin_read_DMA7_NEXT_DESC_PTR() 		bfin_read32(DMA7_NEXT_DESC_PTR)#define bfin_write_DMA7_NEXT_DESC_PTR(val) 	bfin_write32(DMA7_NEXT_DESC_PTR)#define bfin_read_DMA7_START_ADDR() 		bfin_read32(DMA7_START_ADDR)#define bfin_write_DMA7_START_ADDR(val) 	bfin_write32(DMA7_START_ADDR)#define bfin_read_DMA7_CONFIG()			bfin_read16(DMA7_CONFIG)#define bfin_write_DMA7_CONFIG(val)		bfin_write16(DMA7_CONFIG, val)#define bfin_read_DMA7_X_COUNT()		bfin_read16(DMA7_X_COUNT)#define bfin_write_DMA7_X_COUNT(val)		bfin_write16(DMA7_X_COUNT, val)#define bfin_read_DMA7_X_MODIFY()		bfin_read16(DMA7_X_MODIFY)#define bfin_write_DMA7_X_MODIFY(val) 		bfin_write16(DMA7_X_MODIFY)#define bfin_read_DMA7_Y_COUNT()		bfin_read16(DMA7_Y_COUNT)#define bfin_write_DMA7_Y_COUNT(val)		bfin_write16(DMA7_Y_COUNT, val)#define bfin_read_DMA7_Y_MODIFY()		bfin_read16(DMA7_Y_MODIFY)#define bfin_write_DMA7_Y_MODIFY(val) 		bfin_write16(DMA7_Y_MODIFY)#define bfin_read_DMA7_CURR_DESC_PTR() 		bfin_read32(DMA7_CURR_DESC_PTR)#define bfin_write_DMA7_CURR_DESC_PTR(val) 	bfin_write32(DMA7_CURR_DESC_PTR)#define bfin_read_DMA7_CURR_ADDR() 		bfin_read32(DMA7_CURR_ADDR)#define bfin_write_DMA7_CURR_ADDR(val) 		bfin_write32(DMA7_CURR_ADDR)#define bfin_read_DMA7_IRQ_STATUS()		bfin_read16(DMA7_IRQ_STATUS)#define bfin_write_DMA7_IRQ_STATUS(val)		bfin_write16(DMA7_IRQ_STATUS, val)#define bfin_read_DMA7_PERIPHERAL_MAP()		bfin_read16(DMA7_PERIPHERAL_MAP)#define bfin_write_DMA7_PERIPHERAL_MAP(val)	bfin_write16(DMA7_PERIPHERAL_MAP, val)#define bfin_read_DMA7_CURR_X_COUNT()		bfin_read16(DMA7_CURR_X_COUNT)#define bfin_write_DMA7_CURR_X_COUNT(val)	bfin_write16(DMA7_CURR_X_COUNT, val)#define bfin_read_DMA7_CURR_Y_COUNT()		bfin_read16(DMA7_CURR_Y_COUNT)#define bfin_write_DMA7_CURR_Y_COUNT(val)	bfin_write16(DMA7_CURR_Y_COUNT, val)/* DMA Channel 8 Registers */#define bfin_read_DMA8_NEXT_DESC_PTR() 		bfin_read32(DMA8_NEXT_DESC_PTR)#define bfin_write_DMA8_NEXT_DESC_PTR(val) 	bfin_write32(DMA8_NEXT_DESC_PTR)#define bfin_read_DMA8_START_ADDR() 		bfin_read32(DMA8_START_ADDR)#define bfin_write_DMA8_START_ADDR(val) 	bfin_write32(DMA8_START_ADDR)#define bfin_read_DMA8_CONFIG()			bfin_read16(DMA8_CONFIG)#define bfin_write_DMA8_CONFIG(val)		bfin_write16(DMA8_CONFIG, val)#define bfin_read_DMA8_X_COUNT()		bfin_read16(DMA8_X_COUNT)#define bfin_write_DMA8_X_COUNT(val)		bfin_write16(DMA8_X_COUNT, val)#define bfin_read_DMA8_X_MODIFY()		bfin_read16(DMA8_X_MODIFY)#define bfin_write_DMA8_X_MODIFY(val) 		bfin_write16(DMA8_X_MODIFY)#define bfin_read_DMA8_Y_COUNT()		bfin_read16(DMA8_Y_COUNT)
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cdefbf54x_base.h - 源码说明

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