cdefbf54x_base.h

来自「linux 内核源代码」· C头文件 代码 · 共 1,112 行 · 第 1/5 页

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#define bfin_read_TWI0_MASTER_CTRL()		bfin_read16(TWI0_MASTER_CTRL)#define bfin_write_TWI0_MASTER_CTRL(val)	bfin_write16(TWI0_MASTER_CTRL, val)#define bfin_read_TWI0_MASTER_STAT()		bfin_read16(TWI0_MASTER_STAT)#define bfin_write_TWI0_MASTER_STAT(val)	bfin_write16(TWI0_MASTER_STAT, val)#define bfin_read_TWI0_MASTER_ADDR()		bfin_read16(TWI0_MASTER_ADDR)#define bfin_write_TWI0_MASTER_ADDR(val)	bfin_write16(TWI0_MASTER_ADDR, val)#define bfin_read_TWI0_INT_STAT()		bfin_read16(TWI0_INT_STAT)#define bfin_write_TWI0_INT_STAT(val)		bfin_write16(TWI0_INT_STAT, val)#define bfin_read_TWI0_INT_MASK()		bfin_read16(TWI0_INT_MASK)#define bfin_write_TWI0_INT_MASK(val)		bfin_write16(TWI0_INT_MASK, val)#define bfin_read_TWI0_FIFO_CTRL()		bfin_read16(TWI0_FIFO_CTRL)#define bfin_write_TWI0_FIFO_CTRL(val)		bfin_write16(TWI0_FIFO_CTRL, val)#define bfin_read_TWI0_FIFO_STAT()		bfin_read16(TWI0_FIFO_STAT)#define bfin_write_TWI0_FIFO_STAT(val)		bfin_write16(TWI0_FIFO_STAT, val)#define bfin_read_TWI0_XMT_DATA8()		bfin_read16(TWI0_XMT_DATA8)#define bfin_write_TWI0_XMT_DATA8(val)		bfin_write16(TWI0_XMT_DATA8, val)#define bfin_read_TWI0_XMT_DATA16()		bfin_read16(TWI0_XMT_DATA16)#define bfin_write_TWI0_XMT_DATA16(val)		bfin_write16(TWI0_XMT_DATA16, val)#define bfin_read_TWI0_RCV_DATA8()		bfin_read16(TWI0_RCV_DATA8)#define bfin_write_TWI0_RCV_DATA8(val)		bfin_write16(TWI0_RCV_DATA8, val)#define bfin_read_TWI0_RCV_DATA16()		bfin_read16(TWI0_RCV_DATA16)#define bfin_write_TWI0_RCV_DATA16(val)		bfin_write16(TWI0_RCV_DATA16, val)#define bfin_read_TWI_CLKDIV()			bfin_read16(TWI0_CLKDIV)#define bfin_write_TWI_CLKDIV(val)		bfin_write16(TWI0_CLKDIV, val)#define bfin_read_TWI_CONTROL()			bfin_read16(TWI0_CONTROL)#define bfin_write_TWI_CONTROL(val)		bfin_write16(TWI0_CONTROL, val)#define bfin_read_TWI_SLAVE_CTRL()		bfin_read16(TWI0_SLAVE_CTRL)#define bfin_write_TWI_SLAVE_CTRL(val)		bfin_write16(TWI0_SLAVE_CTRL, val)#define bfin_read_TWI_SLAVE_STAT()		bfin_read16(TWI0_SLAVE_STAT)#define bfin_write_TWI_SLAVE_STAT(val)		bfin_write16(TWI0_SLAVE_STAT, val)#define bfin_read_TWI_SLAVE_ADDR()		bfin_read16(TWI0_SLAVE_ADDR)#define bfin_write_TWI_SLAVE_ADDR(val)		bfin_write16(TWI0_SLAVE_ADDR, val)#define bfin_read_TWI_MASTER_CTL()		bfin_read16(TWI0_MASTER_CTRL)#define bfin_write_TWI_MASTER_CTL(val)		bfin_write16(TWI0_MASTER_CTRL, val)#define bfin_read_TWI_MASTER_STAT()		bfin_read16(TWI0_MASTER_STAT)#define bfin_write_TWI_MASTER_STAT(val)		bfin_write16(TWI0_MASTER_STAT, val)#define bfin_read_TWI_MASTER_ADDR()		bfin_read16(TWI0_MASTER_ADDR)#define bfin_write_TWI_MASTER_ADDR(val)		bfin_write16(TWI0_MASTER_ADDR, val)#define bfin_read_TWI_INT_STAT()		bfin_read16(TWI0_INT_STAT)#define bfin_write_TWI_INT_STAT(val)		bfin_write16(TWI0_INT_STAT, val)#define bfin_read_TWI_INT_MASK()		bfin_read16(TWI0_INT_MASK)#define bfin_write_TWI_INT_MASK(val)		bfin_write16(TWI0_INT_MASK, val)#define bfin_read_TWI_FIFO_CTL()		bfin_read16(TWI0_FIFO_CTRL)#define bfin_write_TWI_FIFO_CTL(val)		bfin_write16(TWI0_FIFO_CTRL, val)#define bfin_read_TWI_FIFO_STAT()		bfin_read16(TWI0_FIFO_STAT)#define bfin_write_TWI_FIFO_STAT(val)		bfin_write16(TWI0_FIFO_STAT, val)#define bfin_read_TWI_XMT_DATA8()		bfin_read16(TWI0_XMT_DATA8)#define bfin_write_TWI_XMT_DATA8(val)		bfin_write16(TWI0_XMT_DATA8, val)#define bfin_read_TWI_XMT_DATA16()		bfin_read16(TWI0_XMT_DATA16)#define bfin_write_TWI_XMT_DATA16(val)		bfin_write16(TWI0_XMT_DATA16, val)#define bfin_read_TWI_RCV_DATA8()		bfin_read16(TWI0_RCV_DATA8)#define bfin_write_TWI_RCV_DATA8(val)		bfin_write16(TWI0_RCV_DATA8, val)#define bfin_read_TWI_RCV_DATA16()		bfin_read16(TWI0_RCV_DATA16)#define bfin_write_TWI_RCV_DATA16(val)		bfin_write16(TWI0_RCV_DATA16, val)/* SPORT0 is not defined in the shared file because it is not available on the ADSP-BF542 and ADSP-BF544 bfin_read_()rocessors *//* SPORT1 Registers */#define bfin_read_SPORT1_TCR1()		bfin_read16(SPORT1_TCR1)#define bfin_write_SPORT1_TCR1(val)	bfin_write16(SPORT1_TCR1, val)#define bfin_read_SPORT1_TCR2()		bfin_read16(SPORT1_TCR2)#define bfin_write_SPORT1_TCR2(val)	bfin_write16(SPORT1_TCR2, val)#define bfin_read_SPORT1_TCLKDIV()	bfin_read16(SPORT1_TCLKDIV)#define bfin_write_SPORT1_TCLKDIV(val)	bfin_write16(SPORT1_TCLKDIV, val)#define bfin_read_SPORT1_TFSDIV()	bfin_read16(SPORT1_TFSDIV)#define bfin_write_SPORT1_TFSDIV(val)	bfin_write16(SPORT1_TFSDIV, val)#define bfin_read_SPORT1_TX()		bfin_read32(SPORT1_TX)#define bfin_write_SPORT1_TX(val)	bfin_write32(SPORT1_TX, val)#define bfin_read_SPORT1_RX()		bfin_read32(SPORT1_RX)#define bfin_write_SPORT1_RX(val)	bfin_write32(SPORT1_RX, val)#define bfin_read_SPORT1_RCR1()		bfin_read16(SPORT1_RCR1)#define bfin_write_SPORT1_RCR1(val)	bfin_write16(SPORT1_RCR1, val)#define bfin_read_SPORT1_RCR2()		bfin_read16(SPORT1_RCR2)#define bfin_write_SPORT1_RCR2(val)	bfin_write16(SPORT1_RCR2, val)#define bfin_read_SPORT1_RCLKDIV()	bfin_read16(SPORT1_RCLKDIV)#define bfin_write_SPORT1_RCLKDIV(val)	bfin_write16(SPORT1_RCLKDIV, val)#define bfin_read_SPORT1_RFSDIV()	bfin_read16(SPORT1_RFSDIV)#define bfin_write_SPORT1_RFSDIV(val)	bfin_write16(SPORT1_RFSDIV, val)#define bfin_read_SPORT1_STAT()		bfin_read16(SPORT1_STAT)#define bfin_write_SPORT1_STAT(val)	bfin_write16(SPORT1_STAT, val)#define bfin_read_SPORT1_CHNL()		bfin_read16(SPORT1_CHNL)#define bfin_write_SPORT1_CHNL(val)	bfin_write16(SPORT1_CHNL, val)#define bfin_read_SPORT1_MCMC1()	bfin_read16(SPORT1_MCMC1)#define bfin_write_SPORT1_MCMC1(val)	bfin_write16(SPORT1_MCMC1, val)#define bfin_read_SPORT1_MCMC2()	bfin_read16(SPORT1_MCMC2)#define bfin_write_SPORT1_MCMC2(val)	bfin_write16(SPORT1_MCMC2, val)#define bfin_read_SPORT1_MTCS0()	bfin_read32(SPORT1_MTCS0)#define bfin_write_SPORT1_MTCS0(val)	bfin_write32(SPORT1_MTCS0, val)#define bfin_read_SPORT1_MTCS1()	bfin_read32(SPORT1_MTCS1)#define bfin_write_SPORT1_MTCS1(val)	bfin_write32(SPORT1_MTCS1, val)#define bfin_read_SPORT1_MTCS2()	bfin_read32(SPORT1_MTCS2)#define bfin_write_SPORT1_MTCS2(val)	bfin_write32(SPORT1_MTCS2, val)#define bfin_read_SPORT1_MTCS3()	bfin_read32(SPORT1_MTCS3)#define bfin_write_SPORT1_MTCS3(val)	bfin_write32(SPORT1_MTCS3, val)#define bfin_read_SPORT1_MRCS0()	bfin_read32(SPORT1_MRCS0)#define bfin_write_SPORT1_MRCS0(val)	bfin_write32(SPORT1_MRCS0, val)#define bfin_read_SPORT1_MRCS1()	bfin_read32(SPORT1_MRCS1)#define bfin_write_SPORT1_MRCS1(val)	bfin_write32(SPORT1_MRCS1, val)#define bfin_read_SPORT1_MRCS2()	bfin_read32(SPORT1_MRCS2)#define bfin_write_SPORT1_MRCS2(val)	bfin_write32(SPORT1_MRCS2, val)#define bfin_read_SPORT1_MRCS3()	bfin_read32(SPORT1_MRCS3)#define bfin_write_SPORT1_MRCS3(val)	bfin_write32(SPORT1_MRCS3, val)/* Asynchronous Memory Control Registers */#define bfin_read_EBIU_AMGCTL()		bfin_read16(EBIU_AMGCTL)#define bfin_write_EBIU_AMGCTL(val)	bfin_write16(EBIU_AMGCTL, val)#define bfin_read_EBIU_AMBCTL0()	bfin_read32(EBIU_AMBCTL0)#define bfin_write_EBIU_AMBCTL0(val)	bfin_write32(EBIU_AMBCTL0, val)#define bfin_read_EBIU_AMBCTL1()	bfin_read32(EBIU_AMBCTL1)#define bfin_write_EBIU_AMBCTL1(val)	bfin_write32(EBIU_AMBCTL1, val)#define bfin_read_EBIU_MBSCTL()		bfin_read16(EBIU_MBSCTL)#define bfin_write_EBIU_MBSCTL(val)	bfin_write16(EBIU_MBSCTL, val)#define bfin_read_EBIU_ARBSTAT()	bfin_read32(EBIU_ARBSTAT)#define bfin_write_EBIU_ARBSTAT(val)	bfin_write32(EBIU_ARBSTAT, val)#define bfin_read_EBIU_MODE()		bfin_read32(EBIU_MODE)#define bfin_write_EBIU_MODE(val)	bfin_write32(EBIU_MODE, val)#define bfin_read_EBIU_FCTL()		bfin_read16(EBIU_FCTL)#define bfin_write_EBIU_FCTL(val)	bfin_write16(EBIU_FCTL, val)/* DDR Memory Control Registers */#define bfin_read_EBIU_DDRCTL0()	bfin_read32(EBIU_DDRCTL0)#define bfin_write_EBIU_DDRCTL0(val)	bfin_write32(EBIU_DDRCTL0, val)#define bfin_read_EBIU_DDRCTL1()	bfin_read32(EBIU_DDRCTL1)#define bfin_write_EBIU_DDRCTL1(val)	bfin_write32(EBIU_DDRCTL1, val)#define bfin_read_EBIU_DDRCTL2()	bfin_read32(EBIU_DDRCTL2)#define bfin_write_EBIU_DDRCTL2(val)	bfin_write32(EBIU_DDRCTL2, val)#define bfin_read_EBIU_DDRCTL3()	bfin_read32(EBIU_DDRCTL3)#define bfin_write_EBIU_DDRCTL3(val)	bfin_write32(EBIU_DDRCTL3, val)#define bfin_read_EBIU_DDRQUE()		bfin_read32(EBIU_DDRQUE)#define bfin_write_EBIU_DDRQUE(val)	bfin_write32(EBIU_DDRQUE, val)#define bfin_read_EBIU_ERRADD() 	bfin_read32(EBIU_ERRADD)#define bfin_write_EBIU_ERRADD(val) 	bfin_write32(EBIU_ERRADD)#define bfin_read_EBIU_ERRMST()		bfin_read16(EBIU_ERRMST)#define bfin_write_EBIU_ERRMST(val)	bfin_write16(EBIU_ERRMST, val)#define bfin_read_EBIU_RSTCTL()		bfin_read16(EBIU_RSTCTL)#define bfin_write_EBIU_RSTCTL(val)	bfin_write16(EBIU_RSTCTL, val)/* DDR BankRead and Write Count Registers */#define bfin_read_EBIU_DDRBRC0()	bfin_read32(EBIU_DDRBRC0)#define bfin_write_EBIU_DDRBRC0(val)	bfin_write32(EBIU_DDRBRC0, val)#define bfin_read_EBIU_DDRBRC1()	bfin_read32(EBIU_DDRBRC1)#define bfin_write_EBIU_DDRBRC1(val)	bfin_write32(EBIU_DDRBRC1, val)#define bfin_read_EBIU_DDRBRC2()	bfin_read32(EBIU_DDRBRC2)#define bfin_write_EBIU_DDRBRC2(val)	bfin_write32(EBIU_DDRBRC2, val)#define bfin_read_EBIU_DDRBRC3()	bfin_read32(EBIU_DDRBRC3)#define bfin_write_EBIU_DDRBRC3(val)	bfin_write32(EBIU_DDRBRC3, val)#define bfin_read_EBIU_DDRBRC4()	bfin_read32(EBIU_DDRBRC4)#define bfin_write_EBIU_DDRBRC4(val)	bfin_write32(EBIU_DDRBRC4, val)#define bfin_read_EBIU_DDRBRC5()	bfin_read32(EBIU_DDRBRC5)#define bfin_write_EBIU_DDRBRC5(val)	bfin_write32(EBIU_DDRBRC5, val)#define bfin_read_EBIU_DDRBRC6()	bfin_read32(EBIU_DDRBRC6)#define bfin_write_EBIU_DDRBRC6(val)	bfin_write32(EBIU_DDRBRC6, val)#define bfin_read_EBIU_DDRBRC7()	bfin_read32(EBIU_DDRBRC7)#define bfin_write_EBIU_DDRBRC7(val)	bfin_write32(EBIU_DDRBRC7, val)#define bfin_read_EBIU_DDRBWC0()	bfin_read32(EBIU_DDRBWC0)#define bfin_write_EBIU_DDRBWC0(val)	bfin_write32(EBIU_DDRBWC0, val)#define bfin_read_EBIU_DDRBWC1()	bfin_read32(EBIU_DDRBWC1)#define bfin_write_EBIU_DDRBWC1(val)	bfin_write32(EBIU_DDRBWC1, val)#define bfin_read_EBIU_DDRBWC2()	bfin_read32(EBIU_DDRBWC2)#define bfin_write_EBIU_DDRBWC2(val)	bfin_write32(EBIU_DDRBWC2, val)#define bfin_read_EBIU_DDRBWC3()	bfin_read32(EBIU_DDRBWC3)#define bfin_write_EBIU_DDRBWC3(val)	bfin_write32(EBIU_DDRBWC3, val)#define bfin_read_EBIU_DDRBWC4()	bfin_read32(EBIU_DDRBWC4)#define bfin_write_EBIU_DDRBWC4(val)	bfin_write32(EBIU_DDRBWC4, val)#define bfin_read_EBIU_DDRBWC5()	bfin_read32(EBIU_DDRBWC5)#define bfin_write_EBIU_DDRBWC5(val)	bfin_write32(EBIU_DDRBWC5, val)#define bfin_read_EBIU_DDRBWC6()	bfin_read32(EBIU_DDRBWC6)#define bfin_write_EBIU_DDRBWC6(val)	bfin_write32(EBIU_DDRBWC6, val)#define bfin_read_EBIU_DDRBWC7()	bfin_read32(EBIU_DDRBWC7)#define bfin_write_EBIU_DDRBWC7(val)	bfin_write32(EBIU_DDRBWC7, val)#define bfin_read_EBIU_DDRACCT()	bfin_read32(EBIU_DDRACCT)#define bfin_write_EBIU_DDRACCT(val)	bfin_write32(EBIU_DDRACCT, val)#define bfin_read_EBIU_DDRTACT()	bfin_read32(EBIU_DDRTACT)#define bfin_write_EBIU_DDRTACT(val)	bfin_write32(EBIU_DDRTACT, val)#define bfin_read_EBIU_DDRARCT()	bfin_read32(EBIU_DDRARCT)#define bfin_write_EBIU_DDRARCT(val)	bfin_write32(EBIU_DDRARCT, val)#define bfin_read_EBIU_DDRGC0()		bfin_read32(EBIU_DDRGC0)#define bfin_write_EBIU_DDRGC0(val)	bfin_write32(EBIU_DDRGC0, val)#define bfin_read_EBIU_DDRGC1()		bfin_read32(EBIU_DDRGC1)#define bfin_write_EBIU_DDRGC1(val)	bfin_write32(EBIU_DDRGC1, val)#define bfin_read_EBIU_DDRGC2()		bfin_read32(EBIU_DDRGC2)#define bfin_write_EBIU_DDRGC2(val)	bfin_write32(EBIU_DDRGC2, val)#define bfin_read_EBIU_DDRGC3()		bfin_read32(EBIU_DDRGC3)#define bfin_write_EBIU_DDRGC3(val)	bfin_write32(EBIU_DDRGC3, val)#define bfin_read_EBIU_DDRMCEN()	bfin_read32(EBIU_DDRMCEN)#define bfin_write_EBIU_DDRMCEN(val)	bfin_write32(EBIU_DDRMCEN, val)#define bfin_read_EBIU_DDRMCCL()	bfin_read32(EBIU_DDRMCCL)#define bfin_write_EBIU_DDRMCCL(val)	bfin_write32(EBIU_DDRMCCL, val)/* DMAC0 Registers */#define bfin_read_DMAC0_TCPER()		bfin_read16(DMAC0_TCPER)#define bfin_write_DMAC0_TCPER(val)	bfin_write16(DMAC0_TCPER, val)#define bfin_read_DMAC0_TCCNT()		bfin_read16(DMAC0_TCCNT)#define bfin_write_DMAC0_TCCNT(val)	bfin_write16(DMAC0_TCCNT, val)/* DMA Channel 0 Registers */#define bfin_read_DMA0_NEXT_DESC_PTR() 		bfin_read32(DMA0_NEXT_DESC_PTR)#define bfin_write_DMA0_NEXT_DESC_PTR(val) 	bfin_write32(DMA0_NEXT_DESC_PTR)#define bfin_read_DMA0_START_ADDR() 		bfin_read32(DMA0_START_ADDR)#define bfin_write_DMA0_START_ADDR(val) 	bfin_write32(DMA0_START_ADDR)#define bfin_read_DMA0_CONFIG()			bfin_read16(DMA0_CONFIG)#define bfin_write_DMA0_CONFIG(val)		bfin_write16(DMA0_CONFIG, val)#define bfin_read_DMA0_X_COUNT()		bfin_read16(DMA0_X_COUNT)#define bfin_write_DMA0_X_COUNT(val)		bfin_write16(DMA0_X_COUNT, val)#define bfin_read_DMA0_X_MODIFY()		bfin_read16(DMA0_X_MODIFY)#define bfin_write_DMA0_X_MODIFY(val) 		bfin_write16(DMA0_X_MODIFY)#define bfin_read_DMA0_Y_COUNT()		bfin_read16(DMA0_Y_COUNT)#define bfin_write_DMA0_Y_COUNT(val)		bfin_write16(DMA0_Y_COUNT, val)#define bfin_read_DMA0_Y_MODIFY()		bfin_read16(DMA0_Y_MODIFY)#define bfin_write_DMA0_Y_MODIFY(val) 		bfin_write16(DMA0_Y_MODIFY)#define bfin_read_DMA0_CURR_DESC_PTR() 		bfin_read32(DMA0_CURR_DESC_PTR)#define bfin_write_DMA0_CURR_DESC_PTR(val) 	bfin_write32(DMA0_CURR_DESC_PTR)#define bfin_read_DMA0_CURR_ADDR() 		bfin_read32(DMA0_CURR_ADDR)#define bfin_write_DMA0_CURR_ADDR(val) 		bfin_write32(DMA0_CURR_ADDR)#define bfin_read_DMA0_IRQ_STATUS()		bfin_read16(DMA0_IRQ_STATUS)#define bfin_write_DMA0_IRQ_STATUS(val)		bfin_write16(DMA0_IRQ_STATUS, val)
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cdefbf54x_base.h - 源码说明

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