cdefbf544.h
来自「linux 内核源代码」· C头文件 代码 · 共 979 行 · 第 1/5 页
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/* * File: include/asm-blackfin/mach-bf548/cdefBF544.h * Based on: * Author: * * Created: * Description: * * Rev: * * Modified: * * Bugs: Enter bugs at http://blackfin.uclinux.org/ * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2, or (at your option) * any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; see the file COPYING. * If not, write to the Free Software Foundation, * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */#ifndef _CDEF_BF544_H#define _CDEF_BF544_H/* include all Core registers and bit definitions */#include "defBF544.h"/* include core sbfin_read_()ecific register pointer definitions */#include <asm/mach-common/cdef_LPBlackfin.h>/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF544 *//* include cdefBF54x_base.h for the set of #defines that are common to all ADSP-BF54x bfin_read_()rocessors */#include "cdefBF54x_base.h"/* The following are the #defines needed by ADSP-BF544 that are not in the common header *//* Timer Registers */#define bfin_read_TIMER8_CONFIG() bfin_read16(TIMER8_CONFIG)#define bfin_write_TIMER8_CONFIG(val) bfin_write16(TIMER8_CONFIG, val)#define bfin_read_TIMER8_COUNTER() bfin_read32(TIMER8_COUNTER)#define bfin_write_TIMER8_COUNTER(val) bfin_write32(TIMER8_COUNTER, val)#define bfin_read_TIMER8_PERIOD() bfin_read32(TIMER8_PERIOD)#define bfin_write_TIMER8_PERIOD(val) bfin_write32(TIMER8_PERIOD, val)#define bfin_read_TIMER8_WIDTH() bfin_read32(TIMER8_WIDTH)#define bfin_write_TIMER8_WIDTH(val) bfin_write32(TIMER8_WIDTH, val)#define bfin_read_TIMER9_CONFIG() bfin_read16(TIMER9_CONFIG)#define bfin_write_TIMER9_CONFIG(val) bfin_write16(TIMER9_CONFIG, val)#define bfin_read_TIMER9_COUNTER() bfin_read32(TIMER9_COUNTER)#define bfin_write_TIMER9_COUNTER(val) bfin_write32(TIMER9_COUNTER, val)#define bfin_read_TIMER9_PERIOD() bfin_read32(TIMER9_PERIOD)#define bfin_write_TIMER9_PERIOD(val) bfin_write32(TIMER9_PERIOD, val)#define bfin_read_TIMER9_WIDTH() bfin_read32(TIMER9_WIDTH)#define bfin_write_TIMER9_WIDTH(val) bfin_write32(TIMER9_WIDTH, val)#define bfin_read_TIMER10_CONFIG() bfin_read16(TIMER10_CONFIG)#define bfin_write_TIMER10_CONFIG(val) bfin_write16(TIMER10_CONFIG, val)#define bfin_read_TIMER10_COUNTER() bfin_read32(TIMER10_COUNTER)#define bfin_write_TIMER10_COUNTER(val) bfin_write32(TIMER10_COUNTER, val)#define bfin_read_TIMER10_PERIOD() bfin_read32(TIMER10_PERIOD)#define bfin_write_TIMER10_PERIOD(val) bfin_write32(TIMER10_PERIOD, val)#define bfin_read_TIMER10_WIDTH() bfin_read32(TIMER10_WIDTH)#define bfin_write_TIMER10_WIDTH(val) bfin_write32(TIMER10_WIDTH, val)/* Timer Groubfin_read_() of 3 */#define bfin_read_TIMER_ENABLE1() bfin_read16(TIMER_ENABLE1)#define bfin_write_TIMER_ENABLE1(val) bfin_write16(TIMER_ENABLE1, val)#define bfin_read_TIMER_DISABLE1() bfin_read16(TIMER_DISABLE1)#define bfin_write_TIMER_DISABLE1(val) bfin_write16(TIMER_DISABLE1, val)#define bfin_read_TIMER_STATUS1() bfin_read32(TIMER_STATUS1)#define bfin_write_TIMER_STATUS1(val) bfin_write32(TIMER_STATUS1, val)/* EPPI0 Registers */#define bfin_read_EPPI0_STATUS() bfin_read16(EPPI0_STATUS)#define bfin_write_EPPI0_STATUS(val) bfin_write16(EPPI0_STATUS, val)#define bfin_read_EPPI0_HCOUNT() bfin_read16(EPPI0_HCOUNT)#define bfin_write_EPPI0_HCOUNT(val) bfin_write16(EPPI0_HCOUNT, val)#define bfin_read_EPPI0_HDELAY() bfin_read16(EPPI0_HDELAY)#define bfin_write_EPPI0_HDELAY(val) bfin_write16(EPPI0_HDELAY, val)#define bfin_read_EPPI0_VCOUNT() bfin_read16(EPPI0_VCOUNT)#define bfin_write_EPPI0_VCOUNT(val) bfin_write16(EPPI0_VCOUNT, val)#define bfin_read_EPPI0_VDELAY() bfin_read16(EPPI0_VDELAY)#define bfin_write_EPPI0_VDELAY(val) bfin_write16(EPPI0_VDELAY, val)#define bfin_read_EPPI0_FRAME() bfin_read16(EPPI0_FRAME)#define bfin_write_EPPI0_FRAME(val) bfin_write16(EPPI0_FRAME, val)#define bfin_read_EPPI0_LINE() bfin_read16(EPPI0_LINE)#define bfin_write_EPPI0_LINE(val) bfin_write16(EPPI0_LINE, val)#define bfin_read_EPPI0_CLKDIV() bfin_read16(EPPI0_CLKDIV)#define bfin_write_EPPI0_CLKDIV(val) bfin_write16(EPPI0_CLKDIV, val)#define bfin_read_EPPI0_CONTROL() bfin_read32(EPPI0_CONTROL)#define bfin_write_EPPI0_CONTROL(val) bfin_write32(EPPI0_CONTROL, val)#define bfin_read_EPPI0_FS1W_HBL() bfin_read32(EPPI0_FS1W_HBL)#define bfin_write_EPPI0_FS1W_HBL(val) bfin_write32(EPPI0_FS1W_HBL, val)#define bfin_read_EPPI0_FS1P_AVPL() bfin_read32(EPPI0_FS1P_AVPL)#define bfin_write_EPPI0_FS1P_AVPL(val) bfin_write32(EPPI0_FS1P_AVPL, val)#define bfin_read_EPPI0_FS2W_LVB() bfin_read32(EPPI0_FS2W_LVB)#define bfin_write_EPPI0_FS2W_LVB(val) bfin_write32(EPPI0_FS2W_LVB, val)#define bfin_read_EPPI0_FS2P_LAVF() bfin_read32(EPPI0_FS2P_LAVF)#define bfin_write_EPPI0_FS2P_LAVF(val) bfin_write32(EPPI0_FS2P_LAVF, val)#define bfin_read_EPPI0_CLIP() bfin_read32(EPPI0_CLIP)#define bfin_write_EPPI0_CLIP(val) bfin_write32(EPPI0_CLIP, val)/* Two Wire Interface Registers (TWI1) */#define bfin_read_TWI1_CLKDIV() bfin_read16(TWI1_CLKDIV)#define bfin_write_TWI1_CLKDIV(val) bfin_write16(TWI1_CLKDIV, val)#define bfin_read_TWI1_CONTROL() bfin_read16(TWI1_CONTROL)#define bfin_write_TWI1_CONTROL(val) bfin_write16(TWI1_CONTROL, val)#define bfin_read_TWI1_SLAVE_CTRL() bfin_read16(TWI1_SLAVE_CTRL)#define bfin_write_TWI1_SLAVE_CTRL(val) bfin_write16(TWI1_SLAVE_CTRL, val)#define bfin_read_TWI1_SLAVE_STAT() bfin_read16(TWI1_SLAVE_STAT)#define bfin_write_TWI1_SLAVE_STAT(val) bfin_write16(TWI1_SLAVE_STAT, val)#define bfin_read_TWI1_SLAVE_ADDR() bfin_read16(TWI1_SLAVE_ADDR)#define bfin_write_TWI1_SLAVE_ADDR(val) bfin_write16(TWI1_SLAVE_ADDR, val)#define bfin_read_TWI1_MASTER_CTRL() bfin_read16(TWI1_MASTER_CTRL)#define bfin_write_TWI1_MASTER_CTRL(val) bfin_write16(TWI1_MASTER_CTRL, val)#define bfin_read_TWI1_MASTER_STAT() bfin_read16(TWI1_MASTER_STAT)#define bfin_write_TWI1_MASTER_STAT(val) bfin_write16(TWI1_MASTER_STAT, val)#define bfin_read_TWI1_MASTER_ADDR() bfin_read16(TWI1_MASTER_ADDR)#define bfin_write_TWI1_MASTER_ADDR(val) bfin_write16(TWI1_MASTER_ADDR, val)#define bfin_read_TWI1_INT_STAT() bfin_read16(TWI1_INT_STAT)#define bfin_write_TWI1_INT_STAT(val) bfin_write16(TWI1_INT_STAT, val)#define bfin_read_TWI1_INT_MASK() bfin_read16(TWI1_INT_MASK)#define bfin_write_TWI1_INT_MASK(val) bfin_write16(TWI1_INT_MASK, val)#define bfin_read_TWI1_FIFO_CTRL() bfin_read16(TWI1_FIFO_CTRL)#define bfin_write_TWI1_FIFO_CTRL(val) bfin_write16(TWI1_FIFO_CTRL, val)#define bfin_read_TWI1_FIFO_STAT() bfin_read16(TWI1_FIFO_STAT)#define bfin_write_TWI1_FIFO_STAT(val) bfin_write16(TWI1_FIFO_STAT, val)#define bfin_read_TWI1_XMT_DATA8() bfin_read16(TWI1_XMT_DATA8)#define bfin_write_TWI1_XMT_DATA8(val) bfin_write16(TWI1_XMT_DATA8, val)#define bfin_read_TWI1_XMT_DATA16() bfin_read16(TWI1_XMT_DATA16)#define bfin_write_TWI1_XMT_DATA16(val) bfin_write16(TWI1_XMT_DATA16, val)#define bfin_read_TWI1_RCV_DATA8() bfin_read16(TWI1_RCV_DATA8)#define bfin_write_TWI1_RCV_DATA8(val) bfin_write16(TWI1_RCV_DATA8, val)#define bfin_read_TWI1_RCV_DATA16() bfin_read16(TWI1_RCV_DATA16)#define bfin_write_TWI1_RCV_DATA16(val) bfin_write16(TWI1_RCV_DATA16, val)/* CAN Controller 1 Config 1 Registers */#define bfin_read_CAN1_MC1() bfin_read16(CAN1_MC1)#define bfin_write_CAN1_MC1(val) bfin_write16(CAN1_MC1, val)#define bfin_read_CAN1_MD1() bfin_read16(CAN1_MD1)#define bfin_write_CAN1_MD1(val) bfin_write16(CAN1_MD1, val)#define bfin_read_CAN1_TRS1() bfin_read16(CAN1_TRS1)#define bfin_write_CAN1_TRS1(val) bfin_write16(CAN1_TRS1, val)#define bfin_read_CAN1_TRR1() bfin_read16(CAN1_TRR1)#define bfin_write_CAN1_TRR1(val) bfin_write16(CAN1_TRR1, val)#define bfin_read_CAN1_TA1() bfin_read16(CAN1_TA1)#define bfin_write_CAN1_TA1(val) bfin_write16(CAN1_TA1, val)#define bfin_read_CAN1_AA1() bfin_read16(CAN1_AA1)#define bfin_write_CAN1_AA1(val) bfin_write16(CAN1_AA1, val)#define bfin_read_CAN1_RMP1() bfin_read16(CAN1_RMP1)#define bfin_write_CAN1_RMP1(val) bfin_write16(CAN1_RMP1, val)#define bfin_read_CAN1_RML1() bfin_read16(CAN1_RML1)#define bfin_write_CAN1_RML1(val) bfin_write16(CAN1_RML1, val)#define bfin_read_CAN1_MBTIF1() bfin_read16(CAN1_MBTIF1)#define bfin_write_CAN1_MBTIF1(val) bfin_write16(CAN1_MBTIF1, val)#define bfin_read_CAN1_MBRIF1() bfin_read16(CAN1_MBRIF1)#define bfin_write_CAN1_MBRIF1(val) bfin_write16(CAN1_MBRIF1, val)#define bfin_read_CAN1_MBIM1() bfin_read16(CAN1_MBIM1)#define bfin_write_CAN1_MBIM1(val) bfin_write16(CAN1_MBIM1, val)#define bfin_read_CAN1_RFH1() bfin_read16(CAN1_RFH1)#define bfin_write_CAN1_RFH1(val) bfin_write16(CAN1_RFH1, val)#define bfin_read_CAN1_OPSS1() bfin_read16(CAN1_OPSS1)#define bfin_write_CAN1_OPSS1(val) bfin_write16(CAN1_OPSS1, val)/* CAN Controller 1 Config 2 Registers */#define bfin_read_CAN1_MC2() bfin_read16(CAN1_MC2)#define bfin_write_CAN1_MC2(val) bfin_write16(CAN1_MC2, val)#define bfin_read_CAN1_MD2() bfin_read16(CAN1_MD2)#define bfin_write_CAN1_MD2(val) bfin_write16(CAN1_MD2, val)#define bfin_read_CAN1_TRS2() bfin_read16(CAN1_TRS2)#define bfin_write_CAN1_TRS2(val) bfin_write16(CAN1_TRS2, val)#define bfin_read_CAN1_TRR2() bfin_read16(CAN1_TRR2)#define bfin_write_CAN1_TRR2(val) bfin_write16(CAN1_TRR2, val)#define bfin_read_CAN1_TA2() bfin_read16(CAN1_TA2)#define bfin_write_CAN1_TA2(val) bfin_write16(CAN1_TA2, val)#define bfin_read_CAN1_AA2() bfin_read16(CAN1_AA2)#define bfin_write_CAN1_AA2(val) bfin_write16(CAN1_AA2, val)#define bfin_read_CAN1_RMP2() bfin_read16(CAN1_RMP2)#define bfin_write_CAN1_RMP2(val) bfin_write16(CAN1_RMP2, val)#define bfin_read_CAN1_RML2() bfin_read16(CAN1_RML2)#define bfin_write_CAN1_RML2(val) bfin_write16(CAN1_RML2, val)#define bfin_read_CAN1_MBTIF2() bfin_read16(CAN1_MBTIF2)⌨️ 快捷键说明
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