cdefbf548.h
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/* * File: include/asm-blackfin/mach-bf548/cdefBF548.h * Based on: * Author: * * Created: * Description: * * Rev: * * Modified: * * Bugs: Enter bugs at http://blackfin.uclinux.org/ * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2, or (at your option) * any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; see the file COPYING. * If not, write to the Free Software Foundation, * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */#ifndef _CDEF_BF548_H#define _CDEF_BF548_H/* include all Core registers and bit definitions */#include "defBF548.h"/* include core sbfin_read_()ecific register pointer definitions */#include <asm/mach-common/cdef_LPBlackfin.h>/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF548 *//* include cdefBF54x_base.h for the set of #defines that are common to all ADSP-BF54x bfin_read_()rocessors */#include "cdefBF54x_base.h"/* The following are the #defines needed by ADSP-BF548 that are not in the common header *//* Timer Registers */#define bfin_read_TIMER8_CONFIG() bfin_read16(TIMER8_CONFIG)#define bfin_write_TIMER8_CONFIG(val) bfin_write16(TIMER8_CONFIG, val)#define bfin_read_TIMER8_COUNTER() bfin_read32(TIMER8_COUNTER)#define bfin_write_TIMER8_COUNTER(val) bfin_write32(TIMER8_COUNTER, val)#define bfin_read_TIMER8_PERIOD() bfin_read32(TIMER8_PERIOD)#define bfin_write_TIMER8_PERIOD(val) bfin_write32(TIMER8_PERIOD, val)#define bfin_read_TIMER8_WIDTH() bfin_read32(TIMER8_WIDTH)#define bfin_write_TIMER8_WIDTH(val) bfin_write32(TIMER8_WIDTH, val)#define bfin_read_TIMER9_CONFIG() bfin_read16(TIMER9_CONFIG)#define bfin_write_TIMER9_CONFIG(val) bfin_write16(TIMER9_CONFIG, val)#define bfin_read_TIMER9_COUNTER() bfin_read32(TIMER9_COUNTER)#define bfin_write_TIMER9_COUNTER(val) bfin_write32(TIMER9_COUNTER, val)#define bfin_read_TIMER9_PERIOD() bfin_read32(TIMER9_PERIOD)#define bfin_write_TIMER9_PERIOD(val) bfin_write32(TIMER9_PERIOD, val)#define bfin_read_TIMER9_WIDTH() bfin_read32(TIMER9_WIDTH)#define bfin_write_TIMER9_WIDTH(val) bfin_write32(TIMER9_WIDTH, val)#define bfin_read_TIMER10_CONFIG() bfin_read16(TIMER10_CONFIG)#define bfin_write_TIMER10_CONFIG(val) bfin_write16(TIMER10_CONFIG, val)#define bfin_read_TIMER10_COUNTER() bfin_read32(TIMER10_COUNTER)#define bfin_write_TIMER10_COUNTER(val) bfin_write32(TIMER10_COUNTER, val)#define bfin_read_TIMER10_PERIOD() bfin_read32(TIMER10_PERIOD)#define bfin_write_TIMER10_PERIOD(val) bfin_write32(TIMER10_PERIOD, val)#define bfin_read_TIMER10_WIDTH() bfin_read32(TIMER10_WIDTH)#define bfin_write_TIMER10_WIDTH(val) bfin_write32(TIMER10_WIDTH, val)/* Timer Groubfin_read_() of 3 */#define bfin_read_TIMER_ENABLE1() bfin_read16(TIMER_ENABLE1)#define bfin_write_TIMER_ENABLE1(val) bfin_write16(TIMER_ENABLE1, val)#define bfin_read_TIMER_DISABLE1() bfin_read16(TIMER_DISABLE1)#define bfin_write_TIMER_DISABLE1(val) bfin_write16(TIMER_DISABLE1, val)#define bfin_read_TIMER_STATUS1() bfin_read32(TIMER_STATUS1)#define bfin_write_TIMER_STATUS1(val) bfin_write32(TIMER_STATUS1, val)/* SPORT0 Registers */#define bfin_read_SPORT0_TCR1() bfin_read16(SPORT0_TCR1)#define bfin_write_SPORT0_TCR1(val) bfin_write16(SPORT0_TCR1, val)#define bfin_read_SPORT0_TCR2() bfin_read16(SPORT0_TCR2)#define bfin_write_SPORT0_TCR2(val) bfin_write16(SPORT0_TCR2, val)#define bfin_read_SPORT0_TCLKDIV() bfin_read16(SPORT0_TCLKDIV)#define bfin_write_SPORT0_TCLKDIV(val) bfin_write16(SPORT0_TCLKDIV, val)#define bfin_read_SPORT0_TFSDIV() bfin_read16(SPORT0_TFSDIV)#define bfin_write_SPORT0_TFSDIV(val) bfin_write16(SPORT0_TFSDIV, val)#define bfin_read_SPORT0_TX() bfin_read32(SPORT0_TX)#define bfin_write_SPORT0_TX(val) bfin_write32(SPORT0_TX, val)#define bfin_read_SPORT0_RX() bfin_read32(SPORT0_RX)#define bfin_write_SPORT0_RX(val) bfin_write32(SPORT0_RX, val)#define bfin_read_SPORT0_RCR1() bfin_read16(SPORT0_RCR1)#define bfin_write_SPORT0_RCR1(val) bfin_write16(SPORT0_RCR1, val)#define bfin_read_SPORT0_RCR2() bfin_read16(SPORT0_RCR2)#define bfin_write_SPORT0_RCR2(val) bfin_write16(SPORT0_RCR2, val)#define bfin_read_SPORT0_RCLKDIV() bfin_read16(SPORT0_RCLKDIV)#define bfin_write_SPORT0_RCLKDIV(val) bfin_write16(SPORT0_RCLKDIV, val)#define bfin_read_SPORT0_RFSDIV() bfin_read16(SPORT0_RFSDIV)#define bfin_write_SPORT0_RFSDIV(val) bfin_write16(SPORT0_RFSDIV, val)#define bfin_read_SPORT0_STAT() bfin_read16(SPORT0_STAT)#define bfin_write_SPORT0_STAT(val) bfin_write16(SPORT0_STAT, val)#define bfin_read_SPORT0_CHNL() bfin_read16(SPORT0_CHNL)#define bfin_write_SPORT0_CHNL(val) bfin_write16(SPORT0_CHNL, val)#define bfin_read_SPORT0_MCMC1() bfin_read16(SPORT0_MCMC1)#define bfin_write_SPORT0_MCMC1(val) bfin_write16(SPORT0_MCMC1, val)#define bfin_read_SPORT0_MCMC2() bfin_read16(SPORT0_MCMC2)#define bfin_write_SPORT0_MCMC2(val) bfin_write16(SPORT0_MCMC2, val)#define bfin_read_SPORT0_MTCS0() bfin_read32(SPORT0_MTCS0)#define bfin_write_SPORT0_MTCS0(val) bfin_write32(SPORT0_MTCS0, val)#define bfin_read_SPORT0_MTCS1() bfin_read32(SPORT0_MTCS1)#define bfin_write_SPORT0_MTCS1(val) bfin_write32(SPORT0_MTCS1, val)#define bfin_read_SPORT0_MTCS2() bfin_read32(SPORT0_MTCS2)#define bfin_write_SPORT0_MTCS2(val) bfin_write32(SPORT0_MTCS2, val)#define bfin_read_SPORT0_MTCS3() bfin_read32(SPORT0_MTCS3)#define bfin_write_SPORT0_MTCS3(val) bfin_write32(SPORT0_MTCS3, val)#define bfin_read_SPORT0_MRCS0() bfin_read32(SPORT0_MRCS0)#define bfin_write_SPORT0_MRCS0(val) bfin_write32(SPORT0_MRCS0, val)#define bfin_read_SPORT0_MRCS1() bfin_read32(SPORT0_MRCS1)#define bfin_write_SPORT0_MRCS1(val) bfin_write32(SPORT0_MRCS1, val)#define bfin_read_SPORT0_MRCS2() bfin_read32(SPORT0_MRCS2)#define bfin_write_SPORT0_MRCS2(val) bfin_write32(SPORT0_MRCS2, val)#define bfin_read_SPORT0_MRCS3() bfin_read32(SPORT0_MRCS3)#define bfin_write_SPORT0_MRCS3(val) bfin_write32(SPORT0_MRCS3, val)/* EPPI0 Registers */#define bfin_read_EPPI0_STATUS() bfin_read16(EPPI0_STATUS)#define bfin_write_EPPI0_STATUS(val) bfin_write16(EPPI0_STATUS, val)#define bfin_read_EPPI0_HCOUNT() bfin_read16(EPPI0_HCOUNT)#define bfin_write_EPPI0_HCOUNT(val) bfin_write16(EPPI0_HCOUNT, val)#define bfin_read_EPPI0_HDELAY() bfin_read16(EPPI0_HDELAY)#define bfin_write_EPPI0_HDELAY(val) bfin_write16(EPPI0_HDELAY, val)#define bfin_read_EPPI0_VCOUNT() bfin_read16(EPPI0_VCOUNT)#define bfin_write_EPPI0_VCOUNT(val) bfin_write16(EPPI0_VCOUNT, val)#define bfin_read_EPPI0_VDELAY() bfin_read16(EPPI0_VDELAY)#define bfin_write_EPPI0_VDELAY(val) bfin_write16(EPPI0_VDELAY, val)#define bfin_read_EPPI0_FRAME() bfin_read16(EPPI0_FRAME)#define bfin_write_EPPI0_FRAME(val) bfin_write16(EPPI0_FRAME, val)#define bfin_read_EPPI0_LINE() bfin_read16(EPPI0_LINE)#define bfin_write_EPPI0_LINE(val) bfin_write16(EPPI0_LINE, val)#define bfin_read_EPPI0_CLKDIV() bfin_read16(EPPI0_CLKDIV)#define bfin_write_EPPI0_CLKDIV(val) bfin_write16(EPPI0_CLKDIV, val)#define bfin_read_EPPI0_CONTROL() bfin_read32(EPPI0_CONTROL)#define bfin_write_EPPI0_CONTROL(val) bfin_write32(EPPI0_CONTROL, val)#define bfin_read_EPPI0_FS1W_HBL() bfin_read32(EPPI0_FS1W_HBL)#define bfin_write_EPPI0_FS1W_HBL(val) bfin_write32(EPPI0_FS1W_HBL, val)#define bfin_read_EPPI0_FS1P_AVPL() bfin_read32(EPPI0_FS1P_AVPL)#define bfin_write_EPPI0_FS1P_AVPL(val) bfin_write32(EPPI0_FS1P_AVPL, val)#define bfin_read_EPPI0_FS2W_LVB() bfin_read32(EPPI0_FS2W_LVB)#define bfin_write_EPPI0_FS2W_LVB(val) bfin_write32(EPPI0_FS2W_LVB, val)#define bfin_read_EPPI0_FS2P_LAVF() bfin_read32(EPPI0_FS2P_LAVF)#define bfin_write_EPPI0_FS2P_LAVF(val) bfin_write32(EPPI0_FS2P_LAVF, val)#define bfin_read_EPPI0_CLIP() bfin_read32(EPPI0_CLIP)#define bfin_write_EPPI0_CLIP(val) bfin_write32(EPPI0_CLIP, val)/* UART2 Registers */#define bfin_read_UART2_DLL() bfin_read16(UART2_DLL)#define bfin_write_UART2_DLL(val) bfin_write16(UART2_DLL, val)#define bfin_read_UART2_DLH() bfin_read16(UART2_DLH)#define bfin_write_UART2_DLH(val) bfin_write16(UART2_DLH, val)#define bfin_read_UART2_GCTL() bfin_read16(UART2_GCTL)#define bfin_write_UART2_GCTL(val) bfin_write16(UART2_GCTL, val)#define bfin_read_UART2_LCR() bfin_read16(UART2_LCR)#define bfin_write_UART2_LCR(val) bfin_write16(UART2_LCR, val)#define bfin_read_UART2_MCR() bfin_read16(UART2_MCR)#define bfin_write_UART2_MCR(val) bfin_write16(UART2_MCR, val)#define bfin_read_UART2_LSR() bfin_read16(UART2_LSR)#define bfin_write_UART2_LSR(val) bfin_write16(UART2_LSR, val)#define bfin_read_UART2_MSR() bfin_read16(UART2_MSR)#define bfin_write_UART2_MSR(val) bfin_write16(UART2_MSR, val)#define bfin_read_UART2_SCR() bfin_read16(UART2_SCR)#define bfin_write_UART2_SCR(val) bfin_write16(UART2_SCR, val)#define bfin_read_UART2_IER_SET() bfin_read16(UART2_IER_SET)#define bfin_write_UART2_IER_SET(val) bfin_write16(UART2_IER_SET, val)#define bfin_read_UART2_IER_CLEAR() bfin_read16(UART2_IER_CLEAR)#define bfin_write_UART2_IER_CLEAR(val) bfin_write16(UART2_IER_CLEAR, val)#define bfin_read_UART2_RBR() bfin_read16(UART2_RBR)#define bfin_write_UART2_RBR(val) bfin_write16(UART2_RBR, val)/* Two Wire Interface Registers (TWI1) */#define bfin_read_TWI1_CLKDIV() bfin_read16(TWI1_CLKDIV)#define bfin_write_TWI1_CLKDIV(val) bfin_write16(TWI1_CLKDIV, val)#define bfin_read_TWI1_CONTROL() bfin_read16(TWI1_CONTROL)#define bfin_write_TWI1_CONTROL(val) bfin_write16(TWI1_CONTROL, val)#define bfin_read_TWI1_SLAVE_CTRL() bfin_read16(TWI1_SLAVE_CTRL)#define bfin_write_TWI1_SLAVE_CTRL(val) bfin_write16(TWI1_SLAVE_CTRL, val)#define bfin_read_TWI1_SLAVE_STAT() bfin_read16(TWI1_SLAVE_STAT)#define bfin_write_TWI1_SLAVE_STAT(val) bfin_write16(TWI1_SLAVE_STAT, val)#define bfin_read_TWI1_SLAVE_ADDR() bfin_read16(TWI1_SLAVE_ADDR)#define bfin_write_TWI1_SLAVE_ADDR(val) bfin_write16(TWI1_SLAVE_ADDR, val)#define bfin_read_TWI1_MASTER_CTRL() bfin_read16(TWI1_MASTER_CTRL)#define bfin_write_TWI1_MASTER_CTRL(val) bfin_write16(TWI1_MASTER_CTRL, val)#define bfin_read_TWI1_MASTER_STAT() bfin_read16(TWI1_MASTER_STAT)#define bfin_write_TWI1_MASTER_STAT(val) bfin_write16(TWI1_MASTER_STAT, val)#define bfin_read_TWI1_MASTER_ADDR() bfin_read16(TWI1_MASTER_ADDR)#define bfin_write_TWI1_MASTER_ADDR(val) bfin_write16(TWI1_MASTER_ADDR, val)#define bfin_read_TWI1_INT_STAT() bfin_read16(TWI1_INT_STAT)#define bfin_write_TWI1_INT_STAT(val) bfin_write16(TWI1_INT_STAT, val)#define bfin_read_TWI1_INT_MASK() bfin_read16(TWI1_INT_MASK)#define bfin_write_TWI1_INT_MASK(val) bfin_write16(TWI1_INT_MASK, val)⌨️ 快捷键说明
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