ibm44x.h
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/* * include/asm-ppc/ibm44x.h * * PPC44x definitions * * Matt Porter <mporter@kernel.crashing.org> * * Copyright 2002-2005 MontaVista Software Inc. * * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License as published by the * Free Software Foundation; either version 2 of the License, or (at your * option) any later version. */#ifdef __KERNEL__#ifndef __ASM_IBM44x_H__#define __ASM_IBM44x_H__#ifndef NR_BOARD_IRQS#define NR_BOARD_IRQS 0#endif#define _IO_BASE isa_io_base#define _ISA_MEM_BASE isa_mem_base#define PCI_DRAM_OFFSET pci_dram_offset/* TLB entry offset/size used for pinning kernel lowmem */#define PPC44x_PIN_SHIFT 28#define PPC_PIN_SIZE (1 << PPC44x_PIN_SHIFT)/* Lowest TLB slot consumed by the default pinned TLBs */#define PPC44x_LOW_SLOT 63/* * Least significant 32-bits and extended real page number (ERPN) of * UART0 physical address location for early serial text debug */#if defined(CONFIG_440SP)#define UART0_PHYS_ERPN 1#define UART0_PHYS_IO_BASE 0xf0000200#elif defined(CONFIG_440SPE)#define UART0_PHYS_ERPN 4#define UART0_PHYS_IO_BASE 0xf0000200#elif defined(CONFIG_440EP)#define UART0_PHYS_IO_BASE 0xe0000000#else#define UART0_PHYS_ERPN 1#define UART0_PHYS_IO_BASE 0x40000200#endif/* * XXX This 36-bit trap stuff will move somewhere in syslib/ * when we rework/abstract the PPC44x PCI-X handling -mdp *//* * Standard 4GB "page" definitions */#if defined(CONFIG_440SP)#define PPC44x_IO_PAGE 0x0000000100000000ULL#define PPC44x_PCICFG_PAGE 0x0000000900000000ULL#define PPC44x_PCIIO_PAGE PPC44x_PCICFG_PAGE#define PPC44x_PCIMEM_PAGE 0x0000000a00000000ULL#elif defined(CONFIG_440SPE)#define PPC44x_IO_PAGE 0x0000000400000000ULL#define PPC44x_PCICFG_PAGE 0x0000000c00000000ULL#define PPC44x_PCIIO_PAGE PPC44x_PCICFG_PAGE#define PPC44x_PCIMEM_PAGE 0x0000000d00000000ULL#elif defined(CONFIG_440EP)#define PPC44x_IO_PAGE 0x0000000000000000ULL#define PPC44x_PCICFG_PAGE 0x0000000000000000ULL#define PPC44x_PCIIO_PAGE PPC44x_PCICFG_PAGE#define PPC44x_PCIMEM_PAGE 0x0000000000000000ULL#else#define PPC44x_IO_PAGE 0x0000000100000000ULL#define PPC44x_PCICFG_PAGE 0x0000000200000000ULL#define PPC44x_PCIIO_PAGE PPC44x_PCICFG_PAGE#define PPC44x_PCIMEM_PAGE 0x0000000300000000ULL#endif/* * 36-bit trap ranges */#if defined(CONFIG_440SP) || defined(CONFIG_440SPE)#define PPC44x_IO_LO 0xf0000000UL#define PPC44x_IO_HI 0xf0000fffUL#define PPC44x_PCI0CFG_LO 0x0ec00000UL#define PPC44x_PCI0CFG_HI 0x0ec00007UL#define PPC44x_PCI1CFG_LO 0x1ec00000UL#define PPC44x_PCI1CFG_HI 0x1ec00007UL#define PPC44x_PCI2CFG_LO 0x2ec00000UL#define PPC44x_PCI2CFG_HI 0x2ec00007UL#define PPC44x_PCIMEM_LO 0x80000000UL#define PPC44x_PCIMEM_HI 0xdfffffffUL#elif defined(CONFIG_440EP)#define PPC44x_IO_LO 0xef500000UL#define PPC44x_IO_HI 0xefffffffUL#define PPC44x_PCI0CFG_LO 0xeec00000UL#define PPC44x_PCI0CFG_HI 0xeecfffffUL#define PPC44x_PCIMEM_LO 0xa0000000UL#define PPC44x_PCIMEM_HI 0xdfffffffUL#else#define PPC44x_IO_LO 0x40000000UL#define PPC44x_IO_HI 0x40000fffUL#define PPC44x_PCI0CFG_LO 0x0ec00000UL#define PPC44x_PCI0CFG_HI 0x0ec00007UL#define PPC44x_PCIMEM_LO 0x80002000UL#define PPC44x_PCIMEM_HI 0xffffffffUL#endif/* * The "residual" board information structure the boot loader passes * into the kernel. */#ifndef __ASSEMBLY__/* * DCRN definitions *//* CPRs (440GX and 440SP/440SPe) */#define DCRN_CPR_CONFIG_ADDR 0xc#define DCRN_CPR_CONFIG_DATA 0xd#define DCRN_CPR_CLKUPD 0x0020#define DCRN_CPR_PLLC 0x0040#define DCRN_CPR_PLLD 0x0060#define DCRN_CPR_PRIMAD 0x0080#define DCRN_CPR_PRIMBD 0x00a0#define DCRN_CPR_OPBD 0x00c0#define DCRN_CPR_PERD 0x00e0#define DCRN_CPR_MALD 0x0100/* CPRs read/write helper macros */#define CPR_READ(offset) ({\ mtdcr(DCRN_CPR_CONFIG_ADDR, offset); \ mfdcr(DCRN_CPR_CONFIG_DATA);})#define CPR_WRITE(offset, data) ({\ mtdcr(DCRN_CPR_CONFIG_ADDR, offset); \ mtdcr(DCRN_CPR_CONFIG_DATA, data);})/* SDRs (440GX and 440SP/440SPe) */#define DCRN_SDR_CONFIG_ADDR 0xe#define DCRN_SDR_CONFIG_DATA 0xf#define DCRN_SDR_PFC0 0x4100#define DCRN_SDR_PFC1 0x4101#define DCRN_SDR_PFC1_EPS 0x1c00000#define DCRN_SDR_PFC1_EPS_SHIFT 22#define DCRN_SDR_PFC1_RMII 0x02000000#define DCRN_SDR_MFR 0x4300#define DCRN_SDR_MFR_TAH0 0x80000000 /* TAHOE0 Enable */#define DCRN_SDR_MFR_TAH1 0x40000000 /* TAHOE1 Enable */#define DCRN_SDR_MFR_PCM 0x10000000 /* PPC440GP irq compat mode */#define DCRN_SDR_MFR_ECS 0x08000000 /* EMAC int clk */#define DCRN_SDR_MFR_T0TXFL 0x00080000#define DCRN_SDR_MFR_T0TXFH 0x00040000#define DCRN_SDR_MFR_T1TXFL 0x00020000#define DCRN_SDR_MFR_T1TXFH 0x00010000#define DCRN_SDR_MFR_E0TXFL 0x00008000#define DCRN_SDR_MFR_E0TXFH 0x00004000#define DCRN_SDR_MFR_E0RXFL 0x00002000#define DCRN_SDR_MFR_E0RXFH 0x00001000#define DCRN_SDR_MFR_E1TXFL 0x00000800#define DCRN_SDR_MFR_E1TXFH 0x00000400#define DCRN_SDR_MFR_E1RXFL 0x00000200#define DCRN_SDR_MFR_E1RXFH 0x00000100#define DCRN_SDR_MFR_E2TXFL 0x00000080#define DCRN_SDR_MFR_E2TXFH 0x00000040#define DCRN_SDR_MFR_E2RXFL 0x00000020#define DCRN_SDR_MFR_E2RXFH 0x00000010#define DCRN_SDR_MFR_E3TXFL 0x00000008#define DCRN_SDR_MFR_E3TXFH 0x00000004#define DCRN_SDR_MFR_E3RXFL 0x00000002#define DCRN_SDR_MFR_E3RXFH 0x00000001#define DCRN_SDR_UART0 0x0120#define DCRN_SDR_UART1 0x0121#ifdef CONFIG_440EP#define DCRN_SDR_UART2 0x0122#define DCRN_SDR_UART3 0x0123#define DCRN_SDR_CUST0 0x4000#endif/* SDR read/write helper macros */#define SDR_READ(offset) ({\ mtdcr(DCRN_SDR_CONFIG_ADDR, offset); \ mfdcr(DCRN_SDR_CONFIG_DATA);})#define SDR_WRITE(offset, data) ({\ mtdcr(DCRN_SDR_CONFIG_ADDR, offset); \ mtdcr(DCRN_SDR_CONFIG_DATA,data);})/* DMA (excluding 440SP/440SPe) */#define DCRN_DMA0_BASE 0x100#define DCRN_DMA1_BASE 0x108#define DCRN_DMA2_BASE 0x110#define DCRN_DMA3_BASE 0x118#define DCRN_DMASR_BASE 0x120#define DCRNCAP_DMA_SG 1 /* have DMA scatter/gather capability */#define DCRN_MAL_BASE 0x180#ifdef CONFIG_440EP#define DCRN_DMA2P40_BASE 0x300#define DCRN_DMA2P41_BASE 0x308#define DCRN_DMA2P42_BASE 0x310#define DCRN_DMA2P43_BASE 0x318#define DCRN_DMA2P4SR_BASE 0x320#endif/* UIC */#define DCRN_UIC0_BASE 0xc0#define DCRN_UIC1_BASE 0xd0#define UIC0 DCRN_UIC0_BASE#define UIC1 DCRN_UIC1_BASE#ifdef CONFIG_440SPE#define DCRN_UIC2_BASE 0xe0#define DCRN_UIC3_BASE 0xf0#define UIC2 DCRN_UIC2_BASE#define UIC3 DCRN_UIC3_BASE#else#define DCRN_UIC2_BASE 0x210#define DCRN_UICB_BASE 0x200#define UIC2 DCRN_UIC2_BASE#define UICB DCRN_UICB_BASE#endif#define DCRN_UIC_SR(base) (base + 0x0)#define DCRN_UIC_ER(base) (base + 0x2)#define DCRN_UIC_CR(base) (base + 0x3)#define DCRN_UIC_PR(base) (base + 0x4)#define DCRN_UIC_TR(base) (base + 0x5)#define DCRN_UIC_MSR(base) (base + 0x6)#define DCRN_UIC_VR(base) (base + 0x7)#define DCRN_UIC_VCR(base) (base + 0x8)#define UIC0_UIC1NC 0x00000002#ifdef CONFIG_440SPE#define UIC0_UIC1NC 0x00000002#define UIC0_UIC2NC 0x00200000#define UIC0_UIC3NC 0x00008000#endif#define UICB_UIC0NC 0x40000000#define UICB_UIC1NC 0x10000000#define UICB_UIC2NC 0x04000000/* 440 MAL DCRs */#define DCRN_MALCR(base) (base + 0x0) /* Configuration */#define DCRN_MALESR(base) (base + 0x1) /* Error Status */#define DCRN_MALIER(base) (base + 0x2) /* Interrupt Enable */#define DCRN_MALTXCASR(base) (base + 0x4) /* Tx Channel Active Set */#define DCRN_MALTXCARR(base) (base + 0x5) /* Tx Channel Active Reset */#define DCRN_MALTXEOBISR(base) (base + 0x6) /* Tx End of Buffer Interrupt Status */#define DCRN_MALTXDEIR(base) (base + 0x7) /* Tx Descriptor Error Interrupt */#define DCRN_MALRXCASR(base) (base + 0x10) /* Rx Channel Active Set */#define DCRN_MALRXCARR(base) (base + 0x11) /* Rx Channel Active Reset */#define DCRN_MALRXEOBISR(base) (base + 0x12) /* Rx End of Buffer Interrupt Status */#define DCRN_MALRXDEIR(base) (base + 0x13) /* Rx Descriptor Error Interrupt */#define DCRN_MALTXCTP0R(base) (base + 0x20) /* Channel Tx 0 Channel Table Pointer */#define DCRN_MALTXCTP1R(base) (base + 0x21) /* Channel Tx 1 Channel Table Pointer */#define DCRN_MALTXCTP2R(base) (base + 0x22) /* Channel Tx 2 Channel Table Pointer */#define DCRN_MALTXCTP3R(base) (base + 0x23) /* Channel Tx 3 Channel Table Pointer */#define DCRN_MALRXCTP0R(base) (base + 0x40) /* Channel Rx 0 Channel Table Pointer */#define DCRN_MALRXCTP1R(base) (base + 0x41) /* Channel Rx 1 Channel Table Pointer */#define DCRN_MALRCBS0(base) (base + 0x60) /* Channel Rx 0 Channel Buffer Size */#define DCRN_MALRCBS1(base) (base + 0x61) /* Channel Rx 1 Channel Buffer Size *//* Compatibility DCRN's */#define DCRN_MALRXCTP2R(base) ((base) + 0x42) /* Channel Rx 2 Channel Table Pointer */#define DCRN_MALRXCTP3R(base) ((base) + 0x43) /* Channel Rx 3 Channel Table Pointer */#define DCRN_MALTXCTP4R(base) ((base) + 0x24) /* Channel Tx 4 Channel Table Pointer */#define DCRN_MALTXCTP5R(base) ((base) + 0x25) /* Channel Tx 5 Channel Table Pointer */#define DCRN_MALTXCTP6R(base) ((base) + 0x26) /* Channel Tx 6 Channel Table Pointer */#define DCRN_MALTXCTP7R(base) ((base) + 0x27) /* Channel Tx 7 Channel Table Pointer */#define DCRN_MALRCBS2(base) ((base) + 0x62) /* Channel Rx 2 Channel Buffer Size */#define DCRN_MALRCBS3(base) ((base) + 0x63) /* Channel Rx 3 Channel Buffer Size */#define MALCR_MMSR 0x80000000 /* MAL Software reset */#define MALCR_PLBP_1 0x00400000 /* MAL reqest priority: */#define MALCR_PLBP_2 0x00800000 /* lowsest is 00 */#define MALCR_PLBP_3 0x00C00000 /* highest */#define MALCR_GA 0x00200000 /* Guarded Active Bit */#define MALCR_OA 0x00100000 /* Ordered Active Bit */#define MALCR_PLBLE 0x00080000 /* PLB Lock Error Bit */#define MALCR_PLBLT_1 0x00040000 /* PLB Latency Timer */#define MALCR_PLBLT_2 0x00020000#define MALCR_PLBLT_3 0x00010000#define MALCR_PLBLT_4 0x00008000#ifdef CONFIG_440GP#define MALCR_PLBLT_DEFAULT 0x00330000 /* PLB Latency Timer default */#else#define MALCR_PLBLT_DEFAULT 0x00ff0000 /* PLB Latency Timer default */#endif#define MALCR_PLBB 0x00004000 /* PLB Burst Deactivation Bit */#define MALCR_OPBBL 0x00000080 /* OPB Lock Bit */#define MALCR_EOPIE 0x00000004 /* End Of Packet Interrupt Enable */#define MALCR_LEA 0x00000002 /* Locked Error Active */#define MALCR_MSD 0x00000001 /* MAL Scroll Descriptor Bit *//* DCRN_MALESR */#define MALESR_EVB 0x80000000 /* Error Valid Bit */#define MALESR_CIDRX 0x40000000 /* Channel ID Receive */#define MALESR_DE 0x00100000 /* Descriptor Error */#define MALESR_OEN 0x00080000 /* OPB Non-Fullword Error */#define MALESR_OTE 0x00040000 /* OPB Timeout Error */#define MALESR_OSE 0x00020000 /* OPB Slave Error */#define MALESR_PEIN 0x00010000 /* PLB Bus Error Indication */#define MALESR_DEI 0x00000010 /* Descriptor Error Interrupt */#define MALESR_ONEI 0x00000008 /* OPB Non-Fullword Error Interrupt */#define MALESR_OTEI 0x00000004 /* OPB Timeout Error Interrupt */#define MALESR_OSEI 0x00000002 /* OPB Slace Error Interrupt */#define MALESR_PBEI 0x00000001 /* PLB Bus Error Interrupt *//* DCRN_MALIER */#define MALIER_DE 0x00000010 /* Descriptor Error Interrupt Enable */#define MALIER_NE 0x00000008 /* OPB Non-word Transfer Int Enable */#define MALIER_TE 0x00000004 /* OPB Time Out Error Interrupt Enable */#define MALIER_OPBE 0x00000002 /* OPB Slave Error Interrupt Enable */#define MALIER_PLBE 0x00000001 /* PLB Error Interrupt Enable *//* DCRN_MALTXEOBISR */#define MALOBISR_CH0 0x80000000 /* EOB channel 1 bit */#define MALOBISR_CH2 0x40000000 /* EOB channel 2 bit */#if defined(CONFIG_440SP) || defined(CONFIG_440SPE)/* 440SP/440SPe PLB Arbiter DCRs */#define DCRN_PLB_REVID 0x080 /* PLB Revision ID */#define DCRN_PLB_CCR 0x088 /* PLB Crossbar Control */#define DCRN_PLB0_ACR 0x081 /* PLB Arbiter Control */#define DCRN_PLB0_BESRL 0x082 /* PLB Error Status */#define DCRN_PLB0_BESRH 0x083 /* PLB Error Status */#define DCRN_PLB0_BEARL 0x084 /* PLB Error Address Low */#define DCRN_PLB0_BEARH 0x085 /* PLB Error Address High */#define DCRN_PLB1_ACR 0x089 /* PLB Arbiter Control */#define DCRN_PLB1_BESRL 0x08a /* PLB Error Status */⌨️ 快捷键说明
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