spr-regs.h

linux 内核源代码

#define ESRx_EC_DATA_STORE	0x00000000	/* - data_store_error */
#define ESRx_EC_INSN_ACCESS	0x00000006	/* - instruction_access_error */
#define ESRx_EC_PRIV_INSN	0x00000008	/* - privileged_instruction */
#define ESRx_EC_ILL_INSN	0x0000000a	/* - illegal_instruction */
#define ESRx_EC_MP_EXCEP	0x0000001c	/* - mp_exception */
#define ESRx_EC_DATA_ACCESS	0x00000020	/* - data_access_error */
#define ESRx_EC_DIVISION	0x00000026	/* - division_exception */
#define ESRx_EC_ITLB_MISS	0x00000034	/* - instruction_access_TLB_miss */
#define ESRx_EC_DTLB_MISS	0x00000036	/* - data_access_TLB_miss */
#define ESRx_EC_DATA_ACCESS_DAT	0x0000003a	/* - data_access_DAT_exception */

#define ESR0_IAEC		0x00000100	/* info for instruction-access-exception */
#define ESR0_IAEC_RESV		0x00000000	/* - reserved */
#define ESR0_IAEC_PROT_VIOL	0x00000100	/* - protection violation */

#define ESR0_ATXC		0x00f00000	/* address translation exception code */
#define ESR0_ATXC_MMU_MISS	0x00000000	/* - MMU miss exception and more (?) */
#define ESR0_ATXC_MULTI_DAT	0x00800000	/* - multiple DAT entry hit */
#define ESR0_ATXC_MULTI_SAT	0x00900000	/* - multiple SAT entry hit */
#define ESR0_ATXC_AMRTLB_MISS	0x00a00000	/* - MMU/TLB miss exception */
#define ESR0_ATXC_PRIV_EXCEP	0x00c00000	/* - privilege protection fault */
#define ESR0_ATXC_WP_EXCEP	0x00d00000	/* - write protection fault */

#define ESR0_EAV		0x00000800	/* true if EAR0 register valid */
#define ESR15_EAV		0x00000800	/* true if EAR15 register valid */

/*
 * ESFR1 - Exception Status Valid Flag Register
 */
#define ESFR1_ESR0		0x00000001	/* true if ESR0 is valid */
#define ESFR1_ESR14		0x00004000	/* true if ESR14 is valid */
#define ESFR1_ESR15		0x00008000	/* true if ESR15 is valid */

/*
 * MSR - Media Status Register
 */
#define MSR0_AOVF		0x00000001	/* overflow exception accrued */
#define MSRx_OVF		0x00000002	/* overflow exception detected */
#define MSRx_SIE		0x0000003c	/* last SIMD instruction exception detected */
#define MSRx_SIE_NONE		0x00000000	/* - none detected */
#define MSRx_SIE_FRkHI_ACCk	0x00000020	/* - exception at FRkHI or ACCk */
#define MSRx_SIE_FRkLO_ACCk1	0x00000010	/* - exception at FRkLO or ACCk+1 */
#define MSRx_SIE_FRk1HI_ACCk2	0x00000008	/* - exception at FRk+1HI or ACCk+2 */
#define MSRx_SIE_FRk1LO_ACCk3	0x00000004	/* - exception at FRk+1LO or ACCk+3 */
#define MSR0_MTT		0x00007000	/* type of last media trap detected */
#define MSR0_MTT_NONE		0x00000000	/* - none detected */
#define MSR0_MTT_OVERFLOW	0x00001000	/* - overflow detected */
#define MSR0_HI			0x00c00000	/* hardware implementation */
#define MSR0_HI_ROUNDING	0x00000000	/* - rounding mode */
#define MSR0_HI_NONROUNDING	0x00c00000	/* - non-rounding mode */
#define MSR0_EMCI		0x01000000	/* enable media custom instructions */
#define MSR0_SRDAV		0x10000000	/* select rounding mode of MAVEH */
#define MSR0_SRDAV_RDAV		0x00000000	/* - controlled by MSR.RDAV */
#define MSR0_SRDAV_RD		0x10000000	/* - controlled by MSR.RD */
#define MSR0_RDAV		0x20000000	/* rounding mode of MAVEH */
#define MSR0_RDAV_NEAREST_MI	0x00000000	/* - round to nearest minus */
#define MSR0_RDAV_NEAREST_PL	0x20000000	/* - round to nearest plus */
#define MSR0_RD			0xc0000000	/* rounding mode */
#define MSR0_RD_NEAREST		0x00000000	/* - nearest */
#define MSR0_RD_ZERO		0x40000000	/* - zero */
#define MSR0_RD_POS_INF		0x80000000	/* - postive infinity */
#define MSR0_RD_NEG_INF		0xc0000000	/* - negative infinity */

/*
 * IAMPR0-7 - Instruction Address Mapping Register
 * DAMPR0-7 - Data Address Mapping Register
 */
#define xAMPRx_V		0x00000001	/* register content validity indicator */
#define DAMPRx_WP		0x00000002	/* write protect */
#define DAMPRx_WP_RW		0x00000000	/* - read/write */
#define DAMPRx_WP_RO		0x00000002	/* - read-only */
#define xAMPRx_C		0x00000004	/* cached/uncached */
#define xAMPRx_C_CACHED		0x00000000	/* - cached */
#define xAMPRx_C_UNCACHED	0x00000004	/* - uncached */
#define xAMPRx_S		0x00000008	/* supervisor only */
#define xAMPRx_S_USER		0x00000000	/* - userspace can access */
#define xAMPRx_S_KERNEL		0x00000008	/* - kernel only */
#define xAMPRx_SS		0x000000f0	/* segment size */
#define xAMPRx_SS_16Kb		0x00000000	/* - 16 kilobytes */
#define xAMPRx_SS_64Kb		0x00000010	/* - 64 kilobytes */
#define xAMPRx_SS_256Kb		0x00000020	/* - 256 kilobytes */
#define xAMPRx_SS_1Mb		0x00000030	/* - 1 megabyte */
#define xAMPRx_SS_2Mb		0x00000040	/* - 2 megabytes */
#define xAMPRx_SS_4Mb		0x00000050	/* - 4 megabytes */
#define xAMPRx_SS_8Mb		0x00000060	/* - 8 megabytes */
#define xAMPRx_SS_16Mb		0x00000070	/* - 16 megabytes */
#define xAMPRx_SS_32Mb		0x00000080	/* - 32 megabytes */
#define xAMPRx_SS_64Mb		0x00000090	/* - 64 megabytes */
#define xAMPRx_SS_128Mb		0x000000a0	/* - 128 megabytes */
#define xAMPRx_SS_256Mb		0x000000b0	/* - 256 megabytes */
#define xAMPRx_SS_512Mb		0x000000c0	/* - 512 megabytes */
#define xAMPRx_RESERVED8	0x00000100	/* reserved bit */
#define xAMPRx_NG		0x00000200	/* non-global */
#define xAMPRx_L		0x00000400	/* locked */
#define xAMPRx_M		0x00000800	/* modified */
#define xAMPRx_D		0x00001000	/* DAT entry */
#define xAMPRx_RESERVED13	0x00002000	/* reserved bit */
#define xAMPRx_PPFN		0xfff00000	/* physical page frame number */

#define xAMPRx_V_BIT		0
#define DAMPRx_WP_BIT		1
#define xAMPRx_C_BIT		2
#define xAMPRx_S_BIT		3
#define xAMPRx_RESERVED8_BIT	8
#define xAMPRx_NG_BIT		9
#define xAMPRx_L_BIT		10
#define xAMPRx_M_BIT		11
#define xAMPRx_D_BIT		12
#define xAMPRx_RESERVED13_BIT	13

#define __get_IAMPR(R) ({ unsigned long x; asm volatile("movsg iampr"#R",%0" : "=r"(x)); x; })
#define __get_DAMPR(R) ({ unsigned long x; asm volatile("movsg dampr"#R",%0" : "=r"(x)); x; })

#define __get_IAMLR(R) ({ unsigned long x; asm volatile("movsg iamlr"#R",%0" : "=r"(x)); x; })
#define __get_DAMLR(R) ({ unsigned long x; asm volatile("movsg damlr"#R",%0" : "=r"(x)); x; })

#define __set_IAMPR(R,V) 	do { asm volatile("movgs %0,iampr"#R : : "r"(V)); } while(0)
#define __set_DAMPR(R,V)  	do { asm volatile("movgs %0,dampr"#R : : "r"(V)); } while(0)

#define __set_IAMLR(R,V) 	do { asm volatile("movgs %0,iamlr"#R : : "r"(V)); } while(0)
#define __set_DAMLR(R,V)  	do { asm volatile("movgs %0,damlr"#R : : "r"(V)); } while(0)

#define save_dampr(R, _dampr)					\
do {								\
	asm volatile("movsg dampr"R",%0" : "=r"(_dampr));	\
} while(0)

#define restore_dampr(R, _dampr)			\
do {							\
	asm volatile("movgs %0,dampr"R :: "r"(_dampr));	\
} while(0)

/*
 * AMCR - Address Mapping Control Register
 */
#define AMCR_IAMRN		0x000000ff	/* quantity of IAMPR registers */
#define AMCR_DAMRN		0x0000ff00	/* quantity of DAMPR registers */

/*
 * TTBR - Address Translation Table Base Register
 */
#define __get_TTBR()		({ unsigned long x; asm volatile("movsg ttbr,%0" : "=r"(x)); x; })

/*
 * TPXR - TLB Probe Extend Register
 */
#define TPXR_E			0x00000001
#define TPXR_LMAX_SHIFT		20
#define TPXR_LMAX_SMASK		0xf
#define TPXR_WMAX_SHIFT		24
#define TPXR_WMAX_SMASK		0xf
#define TPXR_WAY_SHIFT		28
#define TPXR_WAY_SMASK		0xf

/*
 * DCR - Debug Control Register
 */
#define DCR_IBCE3		0x00000001	/* break on conditional insn pointed to by IBAR3 */
#define DCR_IBE3		0x00000002	/* break on insn pointed to by IBAR3 */
#define DCR_IBCE1		0x00000004	/* break on conditional insn pointed to by IBAR2 */
#define DCR_IBE1		0x00000008	/* break on insn pointed to by IBAR2 */
#define DCR_IBCE2		0x00000010	/* break on conditional insn pointed to by IBAR1 */
#define DCR_IBE2		0x00000020	/* break on insn pointed to by IBAR1 */
#define DCR_IBCE0		0x00000040	/* break on conditional insn pointed to by IBAR0 */
#define DCR_IBE0		0x00000080	/* break on insn pointed to by IBAR0 */

#define DCR_DDBE1		0x00004000	/* use DBDR1x when checking DBAR1 */
#define DCR_DWBE1		0x00008000	/* break on store to address in DBAR1/DBMR1x */
#define DCR_DRBE1		0x00010000	/* break on load from address in DBAR1/DBMR1x */
#define DCR_DDBE0		0x00020000	/* use DBDR0x when checking DBAR0 */
#define DCR_DWBE0		0x00040000	/* break on store to address in DBAR0/DBMR0x */
#define DCR_DRBE0		0x00080000	/* break on load from address in DBAR0/DBMR0x */

#define DCR_EIM			0x0c000000	/* external interrupt disable */
#define DCR_IBM			0x10000000	/* instruction break disable */
#define DCR_SE			0x20000000	/* single step enable */
#define DCR_EBE			0x40000000	/* exception break enable */

/*
 * BRR - Break Interrupt Request Register
 */
#define BRR_ST			0x00000001	/* single-step detected */
#define BRR_SB			0x00000002	/* break instruction detected */
#define BRR_BB			0x00000004	/* branch with hint detected */
#define BRR_CBB			0x00000008	/* branch to LR detected */
#define BRR_IBx			0x000000f0	/* hardware breakpoint detected */
#define BRR_DBx			0x00000f00	/* hardware watchpoint detected */
#define BRR_DBNEx		0x0000f000	/* ? */
#define BRR_EBTT		0x00ff0000	/* trap type of exception break */
#define BRR_TB			0x10000000	/* external break request detected */
#define BRR_CB			0x20000000	/* ICE break command detected */
#define BRR_EB			0x40000000	/* exception break detected */

/*
 * BPSR - Break PSR Save Register
 */
#define BPSR_BET		0x00000001	/* former PSR.ET */
#define BPSR_BS			0x00001000	/* former PSR.S */

#endif /* _ASM_SPR_REGS_H */