core_cia.h

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#define XLT_GRU_INT_REQ_BITS		0x80003fffUL
#define GRU_INT_REQ_BITS		(alpha_mv.sys.cia.gru_int_req_bits+0)

/*
 * PYXIS interrupt control registers
 */
#define PYXIS_INT_REQ			(IDENT_ADDR + 0x87A0000000UL)
#define PYXIS_INT_MASK			(IDENT_ADDR + 0x87A0000040UL)
#define PYXIS_INT_HILO			(IDENT_ADDR + 0x87A00000C0UL)
#define PYXIS_INT_ROUTE			(IDENT_ADDR + 0x87A0000140UL)
#define PYXIS_GPO			(IDENT_ADDR + 0x87A0000180UL)
#define PYXIS_INT_CNFG			(IDENT_ADDR + 0x87A00001C0UL)
#define PYXIS_RT_COUNT			(IDENT_ADDR + 0x87A0000200UL)
#define PYXIS_INT_TIME			(IDENT_ADDR + 0x87A0000240UL)
#define PYXIS_IIC_CTRL			(IDENT_ADDR + 0x87A00002C0UL)
#define PYXIS_RESET			(IDENT_ADDR + 0x8780000900UL)

/* Offset between ram physical addresses and pci64 DAC bus addresses.  */
#define PYXIS_DAC_OFFSET		(1UL << 40)

/*
 * Data structure for handling CIA machine checks.
 */

/* System-specific info.  */
struct el_CIA_sysdata_mcheck {
	unsigned long	cpu_err0;
	unsigned long	cpu_err1;
	unsigned long	cia_err;
	unsigned long	cia_stat;
	unsigned long	err_mask;
	unsigned long	cia_syn;
	unsigned long	mem_err0;
	unsigned long	mem_err1;
	unsigned long	pci_err0;
	unsigned long	pci_err1;
	unsigned long	pci_err2;
};


#ifdef __KERNEL__

#ifndef __EXTERN_INLINE
/* Do not touch, this should *NOT* be static inline */
#define __EXTERN_INLINE extern inline
#define __IO_EXTERN_INLINE
#endif

/*
 * I/O functions:
 *
 * CIA (the 2117x PCI/memory support chipset for the EV5 (21164)
 * series of processors uses a sparse address mapping scheme to
 * get at PCI memory and I/O.
 */

/*
 * Memory functions.  64-bit and 32-bit accesses are done through
 * dense memory space, everything else through sparse space.
 *
 * For reading and writing 8 and 16 bit quantities we need to
 * go through one of the three sparse address mapping regions
 * and use the HAE_MEM CSR to provide some bits of the address.
 * The following few routines use only sparse address region 1
 * which gives 1Gbyte of accessible space which relates exactly
 * to the amount of PCI memory mapping *into* system address space.
 * See p 6-17 of the specification but it looks something like this:
 *
 * 21164 Address:
 *
 *          3         2         1
 * 9876543210987654321098765432109876543210
 * 1ZZZZ0.PCI.QW.Address............BBLL
 *
 * ZZ = SBZ
 * BB = Byte offset
 * LL = Transfer length
 *
 * PCI Address:
 *
 * 3         2         1
 * 10987654321098765432109876543210
 * HHH....PCI.QW.Address........ 00
 *
 * HHH = 31:29 HAE_MEM CSR
 *
 */

#define vip	volatile int __force *
#define vuip	volatile unsigned int __force *
#define vulp	volatile unsigned long __force *

__EXTERN_INLINE unsigned int cia_ioread8(void __iomem *xaddr)
{
	unsigned long addr = (unsigned long) xaddr;
	unsigned long result, base_and_type;

	if (addr >= CIA_DENSE_MEM)
		base_and_type = CIA_SPARSE_MEM + 0x00;
	else
		base_and_type = CIA_IO + 0x00;

	/* We can use CIA_MEM_R1_MASK for io ports too, since it is large
	   enough to cover all io ports, and smaller than CIA_IO.  */
	addr &= CIA_MEM_R1_MASK;
	result = *(vip) ((addr << 5) + base_and_type);
	return __kernel_extbl(result, addr & 3);
}

__EXTERN_INLINE void cia_iowrite8(u8 b, void __iomem *xaddr)
{
	unsigned long addr = (unsigned long) xaddr;
	unsigned long w, base_and_type;

	if (addr >= CIA_DENSE_MEM)
		base_and_type = CIA_SPARSE_MEM + 0x00;
	else
		base_and_type = CIA_IO + 0x00;

	addr &= CIA_MEM_R1_MASK;
	w = __kernel_insbl(b, addr & 3);
	*(vuip) ((addr << 5) + base_and_type) = w;
}

__EXTERN_INLINE unsigned int cia_ioread16(void __iomem *xaddr)
{
	unsigned long addr = (unsigned long) xaddr;
	unsigned long result, base_and_type;

	if (addr >= CIA_DENSE_MEM)
		base_and_type = CIA_SPARSE_MEM + 0x08;
	else
		base_and_type = CIA_IO + 0x08;

	addr &= CIA_MEM_R1_MASK;
	result = *(vip) ((addr << 5) + base_and_type);
	return __kernel_extwl(result, addr & 3);
}

__EXTERN_INLINE void cia_iowrite16(u16 b, void __iomem *xaddr)
{
	unsigned long addr = (unsigned long) xaddr;
	unsigned long w, base_and_type;

	if (addr >= CIA_DENSE_MEM)
		base_and_type = CIA_SPARSE_MEM + 0x08;
	else
		base_and_type = CIA_IO + 0x08;

	addr &= CIA_MEM_R1_MASK;
	w = __kernel_inswl(b, addr & 3);
	*(vuip) ((addr << 5) + base_and_type) = w;
}

__EXTERN_INLINE unsigned int cia_ioread32(void __iomem *xaddr)
{
	unsigned long addr = (unsigned long) xaddr;
	if (addr < CIA_DENSE_MEM)
		addr = ((addr - CIA_IO) << 5) + CIA_IO + 0x18;
	return *(vuip)addr;
}

__EXTERN_INLINE void cia_iowrite32(u32 b, void __iomem *xaddr)
{
	unsigned long addr = (unsigned long) xaddr;
	if (addr < CIA_DENSE_MEM)
		addr = ((addr - CIA_IO) << 5) + CIA_IO + 0x18;
	*(vuip)addr = b;
}

__EXTERN_INLINE void __iomem *cia_ioportmap(unsigned long addr)
{
	return (void __iomem *)(addr + CIA_IO);
}

__EXTERN_INLINE void __iomem *cia_ioremap(unsigned long addr,
					  unsigned long size)
{
	return (void __iomem *)(addr + CIA_DENSE_MEM);
}

__EXTERN_INLINE int cia_is_ioaddr(unsigned long addr)
{
	return addr >= IDENT_ADDR + 0x8000000000UL;
}

__EXTERN_INLINE int cia_is_mmio(const volatile void __iomem *addr)
{
	return (unsigned long)addr >= CIA_DENSE_MEM;
}

__EXTERN_INLINE void __iomem *cia_bwx_ioportmap(unsigned long addr)
{
	return (void __iomem *)(addr + CIA_BW_IO);
}

__EXTERN_INLINE void __iomem *cia_bwx_ioremap(unsigned long addr,
					      unsigned long size)
{
	return (void __iomem *)(addr + CIA_BW_MEM);
}

__EXTERN_INLINE int cia_bwx_is_ioaddr(unsigned long addr)
{
	return addr >= IDENT_ADDR + 0x8000000000UL;
}

__EXTERN_INLINE int cia_bwx_is_mmio(const volatile void __iomem *addr)
{
	return (unsigned long)addr < CIA_BW_IO;
}

#undef vip
#undef vuip
#undef vulp

#undef __IO_PREFIX
#define __IO_PREFIX		cia
#define cia_trivial_rw_bw	2
#define cia_trivial_rw_lq	1
#define cia_trivial_io_bw	0
#define cia_trivial_io_lq	0
#define cia_trivial_iounmap	1
#include <asm/io_trivial.h>

#undef __IO_PREFIX
#define __IO_PREFIX		cia_bwx
#define cia_bwx_trivial_rw_bw	1
#define cia_bwx_trivial_rw_lq	1
#define cia_bwx_trivial_io_bw	1
#define cia_bwx_trivial_io_lq	1
#define cia_bwx_trivial_iounmap	1
#include <asm/io_trivial.h>

#undef __IO_PREFIX
#ifdef CONFIG_ALPHA_PYXIS
#define __IO_PREFIX		cia_bwx
#else
#define __IO_PREFIX		cia
#endif

#ifdef __IO_EXTERN_INLINE
#undef __EXTERN_INLINE
#undef __IO_EXTERN_INLINE
#endif

#endif /* __KERNEL__ */

#endif /* __ALPHA_CIA__H__ */