netx-regs.h
来自「linux 内核源代码」· C头文件 代码 · 共 411 行 · 第 1/2 页
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#define NETX_GPIO_CFG_MODE_INPUT_CAPTURE_ONCE_RISING (2<<3)#define NETX_GPIO_CFG_MODE_INPUT_CAPTURE_HIGH_LEVEL (3<<3)#define NETX_GPIO_CFG_COUNT_REF_COUNTER0 (0<<5)#define NETX_GPIO_CFG_COUNT_REF_COUNTER1 (1<<5)#define NETX_GPIO_CFG_COUNT_REF_COUNTER2 (2<<5)#define NETX_GPIO_CFG_COUNT_REF_COUNTER3 (3<<5)#define NETX_GPIO_CFG_COUNT_REF_COUNTER4 (4<<5)#define NETX_GPIO_CFG_COUNT_REF_SYSTIME (7<<5)#define NETX_GPIO_COUNTER_CTRL_RUN (1<<0)#define NETX_GPIO_COUNTER_CTRL_SYM (1<<1)#define NETX_GPIO_COUNTER_CTRL_ONCE (1<<2)#define NETX_GPIO_COUNTER_CTRL_IRQ_EN (1<<3)#define NETX_GPIO_COUNTER_CTRL_CNT_EVENT (1<<4)#define NETX_GPIO_COUNTER_CTRL_RST_EN (1<<5)#define NETX_GPIO_COUNTER_CTRL_SEL_EVENT (1<<6)#define NETX_GPIO_COUNTER_CTRL_GPIO_REF /* FIXME */#define GPIO_BIT(gpio) (1<<(gpio))#define COUNTER_BIT(counter) ((1<<16)<<(counter))/******************************* * PIO * *******************************//* Registers */#define NETX_PIO_REG(ofs) __io(NETX_VA_PIO + (ofs))#define NETX_PIO_INPIO NETX_PIO_REG(0x0)#define NETX_PIO_OUTPIO NETX_PIO_REG(0x4)#define NETX_PIO_OEPIO NETX_PIO_REG(0x8)/******************************* * MII Unit * *******************************//* Registers */#define NETX_MIIMU __io(NETX_VA_MIIMU)/* Bits */#define MIIMU_SNRDY (1<<0)#define MIIMU_PREAMBLE (1<<1)#define MIIMU_OPMODE_WRITE (1<<2)#define MIIMU_MDC_PERIOD (1<<3)#define MIIMU_PHY_NRES (1<<4)#define MIIMU_RTA (1<<5)#define MIIMU_REGADDR(adr) (((adr) & 0x1f) << 6)#define MIIMU_PHYADDR(adr) (((adr) & 0x1f) << 11)#define MIIMU_DATA(data) (((data) & 0xffff) << 16)/******************************* * xmac / xpec * *******************************//* XPEC register offsets relative to NETX_VA_XPEC(no) */#define NETX_XPEC_R0_OFS 0x00#define NETX_XPEC_R1_OFS 0x04#define NETX_XPEC_R2_OFS 0x08#define NETX_XPEC_R3_OFS 0x0c#define NETX_XPEC_R4_OFS 0x10#define NETX_XPEC_R5_OFS 0x14#define NETX_XPEC_R6_OFS 0x18#define NETX_XPEC_R7_OFS 0x1c#define NETX_XPEC_RANGE01_OFS 0x20#define NETX_XPEC_RANGE23_OFS 0x24#define NETX_XPEC_RANGE45_OFS 0x28#define NETX_XPEC_RANGE67_OFS 0x2c#define NETX_XPEC_PC_OFS 0x48#define NETX_XPEC_TIMER_OFS(timer) (0x30 + ((timer)<<2))#define NETX_XPEC_IRQ_OFS 0x8c#define NETX_XPEC_SYSTIME_NS_OFS 0x90#define NETX_XPEC_FIFO_DATA_OFS 0x94#define NETX_XPEC_SYSTIME_S_OFS 0x98#define NETX_XPEC_ADC_OFS 0x9c#define NETX_XPEC_URX_COUNT_OFS 0x40#define NETX_XPEC_UTX_COUNT_OFS 0x44#define NETX_XPEC_PC_OFS 0x48#define NETX_XPEC_ZERO_OFS 0x4c#define NETX_XPEC_STATCFG_OFS 0x50#define NETX_XPEC_EC_MASKA_OFS 0x54#define NETX_XPEC_EC_MASKB_OFS 0x58#define NETX_XPEC_EC_MASK0_OFS 0x5c#define NETX_XPEC_EC_MASK8_OFS 0x7c#define NETX_XPEC_EC_MASK9_OFS 0x80#define NETX_XPEC_XPU_HOLD_PC_OFS 0x100#define NETX_XPEC_RAM_START_OFS 0x2000/* Bits */#define XPU_HOLD_PC (1<<0)/* XMAC register offsets relative to NETX_VA_XMAC(no) */#define NETX_XMAC_RPU_PROGRAM_START_OFS 0x000#define NETX_XMAC_RPU_PROGRAM_END_OFS 0x3ff#define NETX_XMAC_TPU_PROGRAM_START_OFS 0x400#define NETX_XMAC_TPU_PROGRAM_END_OFS 0x7ff#define NETX_XMAC_RPU_HOLD_PC_OFS 0xa00#define NETX_XMAC_TPU_HOLD_PC_OFS 0xa04#define NETX_XMAC_STATUS_SHARED0_OFS 0x840#define NETX_XMAC_CONFIG_SHARED0_OFS 0x844#define NETX_XMAC_STATUS_SHARED1_OFS 0x848#define NETX_XMAC_CONFIG_SHARED1_OFS 0x84c#define NETX_XMAC_STATUS_SHARED2_OFS 0x850#define NETX_XMAC_CONFIG_SHARED2_OFS 0x854#define NETX_XMAC_STATUS_SHARED3_OFS 0x858#define NETX_XMAC_CONFIG_SHARED3_OFS 0x85c#define RPU_HOLD_PC (1<<15)#define TPU_HOLD_PC (1<<15)/******************************* * Pointer FIFO * *******************************//* Registers */#define NETX_PFIFO_REG(ofs) __io(NETX_VA_PFIFO + (ofs))#define NETX_PFIFO_BASE(pfifo) NETX_PFIFO_REG(0x00 + ((pfifo)<<2))#define NETX_PFIFO_BORDER_BASE(pfifo) NETX_PFIFO_REG(0x80 + ((pfifo)<<2))#define NETX_PFIFO_RESET NETX_PFIFO_REG(0x100)#define NETX_PFIFO_FULL NETX_PFIFO_REG(0x104)#define NETX_PFIFO_EMPTY NETX_PFIFO_REG(0x108)#define NETX_PFIFO_OVEFLOW NETX_PFIFO_REG(0x10c)#define NETX_PFIFO_UNDERRUN NETX_PFIFO_REG(0x110)#define NETX_PFIFO_FILL_LEVEL(pfifo) NETX_PFIFO_REG(0x180 + ((pfifo)<<2))#define NETX_PFIFO_XPEC_ISR(xpec) NETX_PFIFO_REG(0x400 + ((xpec) << 2))/******************************* * Dual Port Memory * *******************************//* Registers */#define NETX_DPMAS_REG(ofs) __io(NETX_VA_DPMAS + (ofs))#define NETX_DPMAS_SYS_STAT NETX_DPMAS_REG(0x4d8)#define NETX_DPMAS_INT_STAT NETX_DPMAS_REG(0x4e0)#define NETX_DPMAS_INT_EN NETX_DPMAS_REG(0x4f0)#define NETX_DPMAS_IF_CONF0 NETX_DPMAS_REG(0x608)#define NETX_DPMAS_IF_CONF1 NETX_DPMAS_REG(0x60c)#define NETX_DPMAS_EXT_CONFIG(cs) NETX_DPMAS_REG(0x610 + 4 * (cs))#define NETX_DPMAS_IO_MODE0 NETX_DPMAS_REG(0x620) /* I/O 32..63 */#define NETX_DPMAS_DRV_EN0 NETX_DPMAS_REG(0x624)#define NETX_DPMAS_DATA0 NETX_DPMAS_REG(0x628)#define NETX_DPMAS_IO_MODE1 NETX_DPMAS_REG(0x630) /* I/O 64..84 */#define NETX_DPMAS_DRV_EN1 NETX_DPMAS_REG(0x634)#define NETX_DPMAS_DATA1 NETX_DPMAS_REG(0x638)/* Bits */#define NETX_DPMAS_INT_EN_GLB_EN (1<<31)#define NETX_DPMAS_INT_EN_MEM_LCK (1<<30)#define NETX_DPMAS_INT_EN_WDG (1<<29)#define NETX_DPMAS_INT_EN_PIO72 (1<<28)#define NETX_DPMAS_INT_EN_PIO47 (1<<27)#define NETX_DPMAS_INT_EN_PIO40 (1<<26)#define NETX_DPMAS_INT_EN_PIO36 (1<<25)#define NETX_DPMAS_INT_EN_PIO35 (1<<24)#define NETX_DPMAS_IF_CONF0_HIF_DISABLED (0<<28)#define NETX_DPMAS_IF_CONF0_HIF_EXT_BUS (1<<28)#define NETX_DPMAS_IF_CONF0_HIF_UP_8BIT (2<<28)#define NETX_DPMAS_IF_CONF0_HIF_UP_16BIT (3<<28)#define NETX_DPMAS_IF_CONF0_HIF_IO (4<<28)#define NETX_DPMAS_IF_CONF0_WAIT_DRV_PP (1<<14)#define NETX_DPMAS_IF_CONF0_WAIT_DRV_OD (2<<14)#define NETX_DPMAS_IF_CONF0_WAIT_DRV_TRI (3<<14)#define NETX_DPMAS_IF_CONF1_IRQ_POL_PIO35 (1<<26)#define NETX_DPMAS_IF_CONF1_IRQ_POL_PIO36 (1<<27)#define NETX_DPMAS_IF_CONF1_IRQ_POL_PIO40 (1<<28)#define NETX_DPMAS_IF_CONF1_IRQ_POL_PIO47 (1<<29)#define NETX_DPMAS_IF_CONF1_IRQ_POL_PIO72 (1<<30)#define NETX_EXT_CONFIG_TALEWIDTH(x) (((x) & 0x7) << 29)#define NETX_EXT_CONFIG_TADRHOLD(x) (((x) & 0x7) << 26)#define NETX_EXT_CONFIG_TCSON(x) (((x) & 0x7) << 23)#define NETX_EXT_CONFIG_TRDON(x) (((x) & 0x7) << 20)#define NETX_EXT_CONFIG_TWRON(x) (((x) & 0x7) << 17)#define NETX_EXT_CONFIG_TWROFF(x) (((x) & 0x1f) << 12)#define NETX_EXT_CONFIG_TRDWRCYC(x) (((x) & 0x1f) << 7)#define NETX_EXT_CONFIG_WAIT_POL (1<<6)#define NETX_EXT_CONFIG_WAIT_EN (1<<5)#define NETX_EXT_CONFIG_NRD_MODE (1<<4)#define NETX_EXT_CONFIG_DS_MODE (1<<3)#define NETX_EXT_CONFIG_NWR_MODE (1<<2)#define NETX_EXT_CONFIG_16BIT (1<<1)#define NETX_EXT_CONFIG_CS_ENABLE (1<<0)#define NETX_DPMAS_IO_MODE0_WRL (1<<13)#define NETX_DPMAS_IO_MODE0_WAIT (1<<14)#define NETX_DPMAS_IO_MODE0_READY (1<<15)#define NETX_DPMAS_IO_MODE0_CS0 (1<<19)#define NETX_DPMAS_IO_MODE0_EXTRD (1<<20)#define NETX_DPMAS_IO_MODE1_CS2 (1<<15)#define NETX_DPMAS_IO_MODE1_CS1 (1<<16)#define NETX_DPMAS_IO_MODE1_SAMPLE_NPOR (0<<30)#define NETX_DPMAS_IO_MODE1_SAMPLE_100MHZ (1<<30)#define NETX_DPMAS_IO_MODE1_SAMPLE_NPIO36 (2<<30)#define NETX_DPMAS_IO_MODE1_SAMPLE_PIO36 (3<<30)/******************************* * I2C * *******************************/#define NETX_I2C_REG(ofs) __io(NETX_VA_I2C, (ofs))#define NETX_I2C_CTRL NETX_I2C_REG(0x0)#define NETX_I2C_DATA NETX_I2C_REG(0x4)#endif /* __ASM_ARCH_NETX_REGS_H */⌨️ 快捷键说明
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