m532xsim.h

来自「linux 内核源代码」· C头文件 代码 · 共 1,369 行 · 第 1/5 页

/****************************************************************************/

/*
 *	m532xsim.h -- ColdFire 5329 registers
 */

/****************************************************************************/
#ifndef	m532xsim_h
#define	m532xsim_h
/****************************************************************************/

#define MCF_REG32(x) (*(volatile unsigned long  *)(x))
#define MCF_REG16(x) (*(volatile unsigned short *)(x))
#define MCF_REG08(x) (*(volatile unsigned char  *)(x))

#define MCFINT_VECBASE      64
#define MCFINT_UART0        26          /* Interrupt number for UART0 */
#define MCFINT_UART1        27          /* Interrupt number for UART1 */

#define MCF_WTM_WCR	MCF_REG16(0xFC098000)

/*
 *	Define the 532x SIM register set addresses.
 */
#define	MCFSIM_IPRL		0xFC048004
#define	MCFSIM_IPRH		0xFC048000
#define	MCFSIM_IPR		MCFSIM_IPRL
#define	MCFSIM_IMRL		0xFC04800C
#define	MCFSIM_IMRH		0xFC048008
#define	MCFSIM_IMR		MCFSIM_IMRL
#define	MCFSIM_ICR0		0xFC048040	
#define	MCFSIM_ICR1		0xFC048041	
#define	MCFSIM_ICR2		0xFC048042	
#define	MCFSIM_ICR3		0xFC048043	
#define	MCFSIM_ICR4		0xFC048044	
#define	MCFSIM_ICR5		0xFC048045	
#define	MCFSIM_ICR6		0xFC048046	
#define	MCFSIM_ICR7		0xFC048047	
#define	MCFSIM_ICR8		0xFC048048	
#define	MCFSIM_ICR9		0xFC048049	
#define	MCFSIM_ICR10		0xFC04804A
#define	MCFSIM_ICR11		0xFC04804B

/*
 *	Some symbol defines for the above...
 */
#define	MCFSIM_SWDICR		MCFSIM_ICR0	/* Watchdog timer ICR */
#define	MCFSIM_TIMER1ICR	MCFSIM_ICR1	/* Timer 1 ICR */
#define	MCFSIM_TIMER2ICR	MCFSIM_ICR2	/* Timer 2 ICR */
#define	MCFSIM_UART1ICR		MCFSIM_ICR4	/* UART 1 ICR */
#define	MCFSIM_UART2ICR		MCFSIM_ICR5	/* UART 2 ICR */
#define	MCFSIM_DMA0ICR		MCFSIM_ICR6	/* DMA 0 ICR */
#define	MCFSIM_DMA1ICR		MCFSIM_ICR7	/* DMA 1 ICR */
#define	MCFSIM_DMA2ICR		MCFSIM_ICR8	/* DMA 2 ICR */
#define	MCFSIM_DMA3ICR		MCFSIM_ICR9	/* DMA 3 ICR */


#define	MCFSIM_IMR_MASKALL	0xFFFFFFFF	/* All SIM intr sources */

#define MCFSIM_IMR_SIMR0	0xFC04801C
#define MCFSIM_IMR_SIMR1	0xFC04C01C
#define MCFSIM_IMR_CIMR0	0xFC04801D
#define MCFSIM_IMR_CIMR1	0xFC04C01D

#define MCFSIM_ICR_TIMER1	(0xFC048040+32)
#define MCFSIM_ICR_TIMER2	(0xFC048040+33)


/*
 *	Macro to set IMR register. It is 32 bits on the 5307.
 */
#define	mcf_getimr()		\
	*((volatile unsigned long *) (MCF_MBAR + MCFSIM_IMR))

#define	mcf_setimr(imr)		\
	*((volatile unsigned long *) (MCF_MBAR + MCFSIM_IMR)) = (imr);

#define	mcf_getipr()		\
	*((volatile unsigned long *) (MCF_MBAR + MCFSIM_IPR))

#define	mcf_getiprl()		\
	*((volatile unsigned long *) (MCF_MBAR + MCFSIM_IPRL))

#define	mcf_getiprh()		\
	*((volatile unsigned long *) (MCF_MBAR + MCFSIM_IPRH))


#define mcf_enable_irq0(irq)		\
	*((volatile unsigned char*) (MCFSIM_IMR_CIMR0)) = (irq);

#define mcf_enable_irq1(irq)		\
	*((volatile unsigned char*) (MCFSIM_IMR_CIMR1)) = (irq);

#define mcf_disable_irq0(irq)		\
	*((volatile unsigned char*) (MCFSIM_IMR_SIMR0)) = (irq);

#define mcf_disable_irq1(irq)		\
	*((volatile unsigned char*) (MCFSIM_IMR_SIMR1)) = (irq);

/*
 *	Define the Cache register flags.
 */
#define	CACR_EC			(1<<31)
#define	CACR_ESB		(1<<29)
#define	CACR_DPI		(1<<28)
#define	CACR_HLCK		(1<<27)
#define	CACR_CINVA		(1<<24)
#define	CACR_DNFB		(1<<10)
#define	CACR_DCM_WTHRU		(0<<8)
#define	CACR_DCM_WBACK		(1<<8)
#define	CACR_DCM_OFF_PRE	(2<<8)
#define	CACR_DCM_OFF_IMP	(3<<8)
#define	CACR_DW			(1<<5)

#define	ACR_BASE_POS		24
#define	ACR_MASK_POS		16
#define	ACR_ENABLE		(1<<15)
#define	ACR_USER		(0<<13)
#define	ACR_SUPER		(1<<13)
#define	ACR_ANY			(2<<13)
#define	ACR_CM_WTHRU		(0<<5)
#define	ACR_CM_WBACK		(1<<5)
#define	ACR_CM_OFF_PRE		(2<<5)
#define	ACR_CM_OFF_IMP		(3<<5)
#define	ACR_WPROTECT		(1<<2)

/*********************************************************************
 *
 * Inter-IC (I2C) Module
 *
 *********************************************************************/

/* Read/Write access macros for general use */
#define MCF532x_I2C_I2ADR       (volatile u8 *) (0xFC058000) // Address 
#define MCF532x_I2C_I2FDR       (volatile u8 *) (0xFC058004) // Freq Divider
#define MCF532x_I2C_I2CR        (volatile u8 *) (0xFC058008) // Control
#define MCF532x_I2C_I2SR        (volatile u8 *) (0xFC05800C) // Status
#define MCF532x_I2C_I2DR        (volatile u8 *) (0xFC058010) // Data I/O

/* Bit level definitions and macros */
#define MCF532x_I2C_I2ADR_ADDR(x)                       (((x)&0x7F)<<0x01)

#define MCF532x_I2C_I2FDR_IC(x)                         (((x)&0x3F))

#define MCF532x_I2C_I2CR_IEN    (0x80)	// I2C enable
#define MCF532x_I2C_I2CR_IIEN   (0x40)  // interrupt enable
#define MCF532x_I2C_I2CR_MSTA   (0x20)  // master/slave mode
#define MCF532x_I2C_I2CR_MTX    (0x10)  // transmit/receive mode
#define MCF532x_I2C_I2CR_TXAK   (0x08)  // transmit acknowledge enable
#define MCF532x_I2C_I2CR_RSTA   (0x04)  // repeat start

#define MCF532x_I2C_I2SR_ICF    (0x80)  // data transfer bit
#define MCF532x_I2C_I2SR_IAAS   (0x40)  // I2C addressed as a slave
#define MCF532x_I2C_I2SR_IBB    (0x20)  // I2C bus busy
#define MCF532x_I2C_I2SR_IAL    (0x10)  // aribitration lost
#define MCF532x_I2C_I2SR_SRW    (0x04)  // slave read/write
#define MCF532x_I2C_I2SR_IIF    (0x02)  // I2C interrupt
#define MCF532x_I2C_I2SR_RXAK   (0x01)  // received acknowledge

#define MCF532x_PAR_FECI2C	(volatile u8 *) (0xFC0A4053)


/*
 *	The M5329EVB board needs a help getting its devices initialized 
 *	at kernel start time if dBUG doesn't set it up (for example 
 *	it is not used), so we need to do it manually.
 */
#ifdef __ASSEMBLER__
.macro m5329EVB_setup
	movel	#0xFC098000, %a7
	movel	#0x0, (%a7)
#define CORE_SRAM	0x80000000	
#define CORE_SRAM_SIZE	0x8000
	movel	#CORE_SRAM, %d0
	addl	#0x221, %d0
	movec	%d0,%RAMBAR1
	movel	#CORE_SRAM, %sp
	addl	#CORE_SRAM_SIZE, %sp
	jsr	sysinit
.endm
#define	PLATFORM_SETUP	m5329EVB_setup

#endif /* __ASSEMBLER__ */

/*********************************************************************
 *
 * Chip Configuration Module (CCM)
 *
 *********************************************************************/

/* Register read/write macros */
#define MCF_CCM_CCR               MCF_REG16(0xFC0A0004)
#define MCF_CCM_RCON              MCF_REG16(0xFC0A0008)
#define MCF_CCM_CIR               MCF_REG16(0xFC0A000A)
#define MCF_CCM_MISCCR            MCF_REG16(0xFC0A0010)
#define MCF_CCM_CDR               MCF_REG16(0xFC0A0012)
#define MCF_CCM_UHCSR             MCF_REG16(0xFC0A0014)
#define MCF_CCM_UOCSR             MCF_REG16(0xFC0A0016)

/* Bit definitions and macros for MCF_CCM_CCR */
#define MCF_CCM_CCR_RESERVED      (0x0001)
#define MCF_CCM_CCR_PLL_MODE      (0x0003)
#define MCF_CCM_CCR_OSC_MODE      (0x0005)
#define MCF_CCM_CCR_BOOTPS(x)     (((x)&0x0003)<<3|0x0001)
#define MCF_CCM_CCR_LOAD          (0x0021)
#define MCF_CCM_CCR_LIMP          (0x0041)
#define MCF_CCM_CCR_CSC(x)        (((x)&0x0003)<<8|0x0001)

/* Bit definitions and macros for MCF_CCM_RCON */
#define MCF_CCM_RCON_RESERVED     (0x0001)
#define MCF_CCM_RCON_PLL_MODE     (0x0003)
#define MCF_CCM_RCON_OSC_MODE     (0x0005)
#define MCF_CCM_RCON_BOOTPS(x)    (((x)&0x0003)<<3|0x0001)
#define MCF_CCM_RCON_LOAD         (0x0021)
#define MCF_CCM_RCON_LIMP         (0x0041)
#define MCF_CCM_RCON_CSC(x)       (((x)&0x0003)<<8|0x0001)

/* Bit definitions and macros for MCF_CCM_CIR */
#define MCF_CCM_CIR_PRN(x)        (((x)&0x003F)<<0)
#define MCF_CCM_CIR_PIN(x)        (((x)&0x03FF)<<6)

/* Bit definitions and macros for MCF_CCM_MISCCR */
#define MCF_CCM_MISCCR_USBSRC     (0x0001)
#define MCF_CCM_MISCCR_USBDIV     (0x0002)
#define MCF_CCM_MISCCR_SSI_SRC    (0x0010)
#define MCF_CCM_MISCCR_TIM_DMA   (0x0020)
#define MCF_CCM_MISCCR_SSI_PUS    (0x0040)
#define MCF_CCM_MISCCR_SSI_PUE    (0x0080)
#define MCF_CCM_MISCCR_LCD_CHEN   (0x0100)
#define MCF_CCM_MISCCR_LIMP       (0x1000)
#define MCF_CCM_MISCCR_PLL_LOCK   (0x2000)

/* Bit definitions and macros for MCF_CCM_CDR */
#define MCF_CCM_CDR_SSIDIV(x)     (((x)&0x000F)<<0)
#define MCF_CCM_CDR_LPDIV(x)      (((x)&0x000F)<<8)

/* Bit definitions and macros for MCF_CCM_UHCSR */
#define MCF_CCM_UHCSR_XPDE        (0x0001)
#define MCF_CCM_UHCSR_UHMIE       (0x0002)
#define MCF_CCM_UHCSR_WKUP        (0x0004)
#define MCF_CCM_UHCSR_PORTIND(x)  (((x)&0x0003)<<14)

/* Bit definitions and macros for MCF_CCM_UOCSR */
#define MCF_CCM_UOCSR_XPDE        (0x0001)
#define MCF_CCM_UOCSR_UOMIE       (0x0002)
#define MCF_CCM_UOCSR_WKUP        (0x0004)
#define MCF_CCM_UOCSR_PWRFLT      (0x0008)
#define MCF_CCM_UOCSR_SEND        (0x0010)
#define MCF_CCM_UOCSR_VVLD        (0x0020)
#define MCF_CCM_UOCSR_BVLD        (0x0040)
#define MCF_CCM_UOCSR_AVLD        (0x0080)
#define MCF_CCM_UOCSR_DPPU        (0x0100)
#define MCF_CCM_UOCSR_DCR_VBUS    (0x0200)
#define MCF_CCM_UOCSR_CRG_VBUS    (0x0400)
#define MCF_CCM_UOCSR_DRV_VBUS    (0x0800)
#define MCF_CCM_UOCSR_DMPD        (0x1000)
#define MCF_CCM_UOCSR_DPPD        (0x2000)
#define MCF_CCM_UOCSR_PORTIND(x)  (((x)&0x0003)<<14)

/*********************************************************************
 *
 * DMA Timers (DTIM)
 *
 *********************************************************************/

/* Register read/write macros */
#define MCF_DTIM0_DTMR           MCF_REG16(0xFC070000)
#define MCF_DTIM0_DTXMR          MCF_REG08(0xFC070002)
#define MCF_DTIM0_DTER           MCF_REG08(0xFC070003)
#define MCF_DTIM0_DTRR           MCF_REG32(0xFC070004)
#define MCF_DTIM0_DTCR           MCF_REG32(0xFC070008)
#define MCF_DTIM0_DTCN           MCF_REG32(0xFC07000C)
#define MCF_DTIM1_DTMR           MCF_REG16(0xFC074000)
#define MCF_DTIM1_DTXMR          MCF_REG08(0xFC074002)