au1000.h

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#define IC0_CFG2CLR                0xB0400054

#define IC0_REQ0INT                0xB0400054
#define IC0_SRCRD                  0xB0400058
#define IC0_SRCSET                 0xB0400058
#define IC0_SRCCLR                 0xB040005C
#define IC0_REQ1INT                0xB040005C

#define IC0_ASSIGNRD               0xB0400060
#define IC0_ASSIGNSET              0xB0400060
#define IC0_ASSIGNCLR              0xB0400064

#define IC0_WAKERD                 0xB0400068
#define IC0_WAKESET                0xB0400068
#define IC0_WAKECLR                0xB040006C

#define IC0_MASKRD                 0xB0400070
#define IC0_MASKSET                0xB0400070
#define IC0_MASKCLR                0xB0400074

#define IC0_RISINGRD               0xB0400078
#define IC0_RISINGCLR              0xB0400078
#define IC0_FALLINGRD              0xB040007C
#define IC0_FALLINGCLR             0xB040007C

#define IC0_TESTBIT                0xB0400080

/* Interrupt Controller 1 */
#define IC1_CFG0RD                 0xB1800040
#define IC1_CFG0SET                0xB1800040
#define IC1_CFG0CLR                0xB1800044

#define IC1_CFG1RD                 0xB1800048
#define IC1_CFG1SET                0xB1800048
#define IC1_CFG1CLR                0xB180004C

#define IC1_CFG2RD                 0xB1800050
#define IC1_CFG2SET                0xB1800050
#define IC1_CFG2CLR                0xB1800054

#define IC1_REQ0INT                0xB1800054
#define IC1_SRCRD                  0xB1800058
#define IC1_SRCSET                 0xB1800058
#define IC1_SRCCLR                 0xB180005C
#define IC1_REQ1INT                0xB180005C

#define IC1_ASSIGNRD               0xB1800060
#define IC1_ASSIGNSET              0xB1800060
#define IC1_ASSIGNCLR              0xB1800064

#define IC1_WAKERD                 0xB1800068
#define IC1_WAKESET                0xB1800068
#define IC1_WAKECLR                0xB180006C

#define IC1_MASKRD                 0xB1800070
#define IC1_MASKSET                0xB1800070
#define IC1_MASKCLR                0xB1800074

#define IC1_RISINGRD               0xB1800078
#define IC1_RISINGCLR              0xB1800078
#define IC1_FALLINGRD              0xB180007C
#define IC1_FALLINGCLR             0xB180007C

#define IC1_TESTBIT                0xB1800080

/* Interrupt Configuration Modes */
#define INTC_INT_DISABLED                0
#define INTC_INT_RISE_EDGE             0x1
#define INTC_INT_FALL_EDGE             0x2
#define INTC_INT_RISE_AND_FALL_EDGE    0x3
#define INTC_INT_HIGH_LEVEL            0x5
#define INTC_INT_LOW_LEVEL             0x6
#define INTC_INT_HIGH_AND_LOW_LEVEL    0x7

/* Interrupt Numbers */
/* Au1000 */
#ifdef CONFIG_SOC_AU1000
enum soc_au1000_ints {
	AU1000_FIRST_INT	= MIPS_CPU_IRQ_BASE + 8,
	AU1000_UART0_INT	= AU1000_FIRST_INT,
	AU1000_UART1_INT,				/* au1000 */
	AU1000_UART2_INT,				/* au1000 */
	AU1000_UART3_INT,
	AU1000_SSI0_INT,				/* au1000 */
	AU1000_SSI1_INT,				/* au1000 */
	AU1000_DMA_INT_BASE,

	AU1000_TOY_INT		= AU1000_FIRST_INT + 14,
	AU1000_TOY_MATCH0_INT,
	AU1000_TOY_MATCH1_INT,
	AU1000_TOY_MATCH2_INT,
	AU1000_RTC_INT,
	AU1000_RTC_MATCH0_INT,
	AU1000_RTC_MATCH1_INT,
	AU1000_RTC_MATCH2_INT,
	AU1000_IRDA_TX_INT,				/* au1000 */
	AU1000_IRDA_RX_INT,				/* au1000 */
	AU1000_USB_DEV_REQ_INT,
	AU1000_USB_DEV_SUS_INT,
	AU1000_USB_HOST_INT,
	AU1000_ACSYNC_INT,
	AU1000_MAC0_DMA_INT,
	AU1000_MAC1_DMA_INT,
	AU1000_I2S_UO_INT,				/* au1000 */
	AU1000_AC97C_INT,
	AU1000_GPIO_0,
	AU1000_GPIO_1,
	AU1000_GPIO_2,
	AU1000_GPIO_3,
	AU1000_GPIO_4,
	AU1000_GPIO_5,
	AU1000_GPIO_6,
	AU1000_GPIO_7,
	AU1000_GPIO_8,
	AU1000_GPIO_9,
	AU1000_GPIO_10,
	AU1000_GPIO_11,
	AU1000_GPIO_12,
	AU1000_GPIO_13,
	AU1000_GPIO_14,
	AU1000_GPIO_15,
	AU1000_GPIO_16,
	AU1000_GPIO_17,
	AU1000_GPIO_18,
	AU1000_GPIO_19,
	AU1000_GPIO_20,
	AU1000_GPIO_21,
	AU1000_GPIO_22,
	AU1000_GPIO_23,
	AU1000_GPIO_24,
	AU1000_GPIO_25,
	AU1000_GPIO_26,
	AU1000_GPIO_27,
	AU1000_GPIO_28,
	AU1000_GPIO_29,
	AU1000_GPIO_30,
	AU1000_GPIO_31,
};

#define UART0_ADDR                0xB1100000
#define UART1_ADDR                0xB1200000
#define UART2_ADDR                0xB1300000
#define UART3_ADDR                0xB1400000

#define USB_OHCI_BASE             0x10100000 // phys addr for ioremap
#define USB_HOST_CONFIG           0xB017fffc

#define AU1000_ETH0_BASE      0xB0500000
#define AU1000_ETH1_BASE      0xB0510000
#define AU1000_MAC0_ENABLE       0xB0520000
#define AU1000_MAC1_ENABLE       0xB0520004
#define NUM_ETH_INTERFACES 2
#endif /* CONFIG_SOC_AU1000 */

/* Au1500 */
#ifdef CONFIG_SOC_AU1500
enum soc_au1500_ints {
	AU1500_FIRST_INT	= MIPS_CPU_IRQ_BASE + 8,
	AU1500_UART0_INT	= AU1500_FIRST_INT,
	AU1000_PCI_INTA,				/* au1500 */
	AU1000_PCI_INTB,				/* au1500 */
	AU1500_UART3_INT,
	AU1000_PCI_INTC,				/* au1500 */
	AU1000_PCI_INTD,				/* au1500 */
	AU1000_DMA_INT_BASE,

	AU1000_TOY_INT		= AU1500_FIRST_INT + 14,
	AU1000_TOY_MATCH0_INT,
	AU1000_TOY_MATCH1_INT,
	AU1000_TOY_MATCH2_INT,
	AU1000_RTC_INT,
	AU1000_RTC_MATCH0_INT,
	AU1000_RTC_MATCH1_INT,
	AU1000_RTC_MATCH2_INT,
	AU1500_PCI_ERR_INT,
	AU1000_USB_DEV_REQ_INT,
	AU1000_USB_DEV_SUS_INT,
	AU1000_USB_HOST_INT,
	AU1000_ACSYNC_INT,
	AU1500_MAC0_DMA_INT,
	AU1500_MAC1_DMA_INT,
	AU1000_AC97C_INT	= AU1500_FIRST_INT + 31,
	AU1000_GPIO_0,
	AU1000_GPIO_1,
	AU1000_GPIO_2,
	AU1000_GPIO_3,
	AU1000_GPIO_4,
	AU1000_GPIO_5,
	AU1000_GPIO_6,
	AU1000_GPIO_7,
	AU1000_GPIO_8,
	AU1000_GPIO_9,
	AU1000_GPIO_10,
	AU1000_GPIO_11,
	AU1000_GPIO_12,
	AU1000_GPIO_13,
	AU1000_GPIO_14,
	AU1000_GPIO_15,
	AU1500_GPIO_200,
	AU1500_GPIO_201,
	AU1500_GPIO_202,
	AU1500_GPIO_203,
	AU1500_GPIO_20,
	AU1500_GPIO_204,
	AU1500_GPIO_205,
	AU1500_GPIO_23,
	AU1500_GPIO_24,
	AU1500_GPIO_25,
	AU1500_GPIO_26,
	AU1500_GPIO_27,
	AU1500_GPIO_28,
	AU1500_GPIO_206,
	AU1500_GPIO_207,
	AU1500_GPIO_208_215,
};

/* shortcuts */
#define INTA AU1000_PCI_INTA
#define INTB AU1000_PCI_INTB
#define INTC AU1000_PCI_INTC
#define INTD AU1000_PCI_INTD

#define UART0_ADDR                0xB1100000
#define UART3_ADDR                0xB1400000

#define USB_OHCI_BASE             0x10100000 // phys addr for ioremap
#define USB_HOST_CONFIG           0xB017fffc

#define AU1500_ETH0_BASE	  0xB1500000
#define AU1500_ETH1_BASE	  0xB1510000
#define AU1500_MAC0_ENABLE       0xB1520000
#define AU1500_MAC1_ENABLE       0xB1520004
#define NUM_ETH_INTERFACES 2
#endif /* CONFIG_SOC_AU1500 */

/* Au1100 */
#ifdef CONFIG_SOC_AU1100
enum soc_au1100_ints {
	AU1100_FIRST_INT	= MIPS_CPU_IRQ_BASE + 8,
	AU1100_UART0_INT,
	AU1100_UART1_INT,
	AU1100_SD_INT,
	AU1100_UART3_INT,
	AU1000_SSI0_INT,
	AU1000_SSI1_INT,
	AU1000_DMA_INT_BASE,

	AU1000_TOY_INT		= AU1100_FIRST_INT + 14,
	AU1000_TOY_MATCH0_INT,
	AU1000_TOY_MATCH1_INT,
	AU1000_TOY_MATCH2_INT,
	AU1000_RTC_INT,
	AU1000_RTC_MATCH0_INT,
	AU1000_RTC_MATCH1_INT,
	AU1000_RTC_MATCH2_INT,
	AU1000_IRDA_TX_INT,
	AU1000_IRDA_RX_INT,
	AU1000_USB_DEV_REQ_INT,
	AU1000_USB_DEV_SUS_INT,
	AU1000_USB_HOST_INT,
	AU1000_ACSYNC_INT,
	AU1100_MAC0_DMA_INT,
	AU1100_GPIO_208_215,
	AU1100_LCD_INT,
	AU1000_AC97C_INT,
	AU1000_GPIO_0,
	AU1000_GPIO_1,
	AU1000_GPIO_2,
	AU1000_GPIO_3,
	AU1000_GPIO_4,
	AU1000_GPIO_5,
	AU1000_GPIO_6,
	AU1000_GPIO_7,
	AU1000_GPIO_8,
	AU1000_GPIO_9,
	AU1000_GPIO_10,
	AU1000_GPIO_11,
	AU1000_GPIO_12,
	AU1000_GPIO_13,
	AU1000_GPIO_14,
	AU1000_GPIO_15,
	AU1000_GPIO_16,
	AU1000_GPIO_17,
	AU1000_GPIO_18,
	AU1000_GPIO_19,
	AU1000_GPIO_20,
	AU1000_GPIO_21,
	AU1000_GPIO_22,
	AU1000_GPIO_23,
	AU1000_GPIO_24,
	AU1000_GPIO_25,
	AU1000_GPIO_26,
	AU1000_GPIO_27,
	AU1000_GPIO_28,
	AU1000_GPIO_29,
	AU1000_GPIO_30,
	AU1000_GPIO_31,
};

#define UART0_ADDR                0xB1100000
#define UART1_ADDR                0xB1200000
#define UART3_ADDR                0xB1400000

#define USB_OHCI_BASE             0x10100000 // phys addr for ioremap
#define USB_HOST_CONFIG           0xB017fffc

#define AU1100_ETH0_BASE	  0xB0500000
#define AU1100_MAC0_ENABLE       0xB0520000
#define NUM_ETH_INTERFACES 1
#endif /* CONFIG_SOC_AU1100 */

#ifdef CONFIG_SOC_AU1550
enum soc_au1550_ints {
	AU1550_FIRST_INT	= MIPS_CPU_IRQ_BASE + 8,
	AU1550_UART0_INT	= AU1550_FIRST_INT,
	AU1550_PCI_INTA,
	AU1550_PCI_INTB,
	AU1550_DDMA_INT,
	AU1550_CRYPTO_INT,
	AU1550_PCI_INTC,
	AU1550_PCI_INTD,
	AU1550_PCI_RST_INT,
	AU1550_UART1_INT,
	AU1550_UART3_INT,
	AU1550_PSC0_INT,
	AU1550_PSC1_INT,
	AU1550_PSC2_INT,
	AU1550_PSC3_INT,
	AU1000_TOY_INT,
	AU1000_TOY_MATCH0_INT,
	AU1000_TOY_MATCH1_INT,
	AU1000_TOY_MATCH2_INT,
	AU1000_RTC_INT,
	AU1000_RTC_MATCH0_INT,
	AU1000_RTC_MATCH1_INT,
	AU1000_RTC_MATCH2_INT,

	AU1550_NAND_INT			= AU1550_FIRST_INT + 23,
	AU1550_USB_DEV_REQ_INT,
	AU1000_USB_DEV_REQ_INT		= AU1550_USB_DEV_REQ_INT,
	AU1550_USB_DEV_SUS_INT,
	AU1000_USB_DEV_SUS_INT		= AU1550_USB_DEV_SUS_INT,
	AU1550_USB_HOST_INT,
	AU1000_USB_HOST_INT		= AU1550_USB_HOST_INT,
	AU1550_MAC0_DMA_INT,
	AU1550_MAC1_DMA_INT,
	AU1000_GPIO_0			= AU1550_FIRST_INT + 32,
	AU1000_GPIO_1,
	AU1000_GPIO_2,
	AU1000_GPIO_3,
	AU1000_GPIO_4,
	AU1000_GPIO_5,
	AU1000_GPIO_6,
	AU1000_GPIO_7,
	AU1000_GPIO_8,
	AU1000_GPIO_9,
	AU1000_GPIO_10,
	AU1000_GPIO_11,
	AU1000_GPIO_12,
	AU1000_GPIO_13,
	AU1000_GPIO_14,
	AU1000_GPIO_15,
	AU1550_GPIO_200,
	AU1500_GPIO_201_205,			/* Logical or of GPIO201:205 */
	AU1500_GPIO_16,
	AU1500_GPIO_17,
	AU1500_GPIO_20,
	AU1500_GPIO_21,
	AU1500_GPIO_22,
	AU1500_GPIO_23,
	AU1500_GPIO_24,
	AU1500_GPIO_25,
	AU1500_GPIO_26,
	AU1500_GPIO_27,
	AU1500_GPIO_28,
	AU1500_GPIO_206,
	AU1500_GPIO_207,
	AU1500_GPIO_208_218,			/* Logical or of GPIO208:218 */
};

/* shortcuts */
#define INTA AU1550_PCI_INTA
#define INTB AU1550_PCI_INTB
#define INTC AU1550_PCI_INTC
#define INTD AU1550_PCI_INTD

#define UART0_ADDR                0xB1100000
#define UART1_ADDR                0xB1200000
#define UART3_ADDR                0xB1400000

#define USB_OHCI_BASE             0x14020000 // phys addr for ioremap
#define USB_OHCI_LEN              0x00060000
#define USB_HOST_CONFIG           0xB4027ffc

#define AU1550_ETH0_BASE      0xB0500000
#define AU1550_ETH1_BASE      0xB0510000
#define AU1550_MAC0_ENABLE       0xB0520000
#define AU1550_MAC1_ENABLE       0xB0520004
#define NUM_ETH_INTERFACES 2
#endif /* CONFIG_SOC_AU1550 */

#ifdef CONFIG_SOC_AU1200
enum soc_au1200_ints {
	AU1200_FIRST_INT	= MIPS_CPU_IRQ_BASE + 8,
	AU1200_UART0_INT	= AU1200_FIRST_INT,
	AU1200_SWT_INT,
	AU1200_SD_INT,
	AU1200_DDMA_INT,
	AU1200_MAE_BE_INT,
	AU1200_GPIO_200,
	AU1200_GPIO_201,
	AU1200_GPIO_202,
	AU1200_UART1_INT,
	AU1200_MAE_FE_INT,
	AU1200_PSC0_INT,
	AU1200_PSC1_INT,
	AU1200_AES_INT,
	AU1200_CAMERA_INT,
	AU1000_TOY_INT,
	AU1000_TOY_MATCH0_INT,
	AU1000_TOY_MATCH1_INT,
	AU1000_TOY_MATCH2_INT,
	AU1000_RTC_INT,
	AU1000_RTC_MATCH0_INT,
	AU1000_RTC_MATCH1_INT,
	AU1000_RTC_MATCH2_INT,

	AU1200_NAND_INT		= AU1200_FIRST_INT + 23,
	AU1200_GPIO_204,
	AU1200_GPIO_205,
	AU1200_GPIO_206,
	AU1200_GPIO_207,
	AU1200_GPIO_208_215,			/* Logical OR of 208:215 */
	AU1200_USB_INT,
	AU1000_USB_HOST_INT	= AU1200_USB_INT,
	AU1200_LCD_INT,
	AU1200_MAE_BOTH_INT,
	AU1000_GPIO_0,
	AU1000_GPIO_1,
	AU1000_GPIO_2,
	AU1000_GPIO_3,
	AU1000_GPIO_4,
	AU1000_GPIO_5,
	AU1000_GPIO_6,
	AU1000_GPIO_7,
	AU1000_GPIO_8,
	AU1000_GPIO_9,
	AU1000_GPIO_10,
	AU1000_GPIO_11,
	AU1000_GPIO_12,