ariadne.h

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#define DXMT2PD		0x1000	/* Disable Transmit Two Part Deferral */
#define EMBA		0x0800	/* Enable Modified Back-off Algorithm */


    /*
     *	Bit definitions for CSR4 (Test and Features Control)
     *
     *	These values are already swap()ed!!
     */

#define ENTST		0x0080	/* Enable Test Mode */
#define DMAPLUS		0x0040	/* Disable Burst Transaction Counter */
#define TIMER		0x0020	/* Timer Enable Register */
#define DPOLL		0x0010	/* Disable Transmit Polling */
#define APAD_XMT	0x0008	/* Auto Pad Transmit */
#define ASTRP_RCV	0x0004	/* Auto Pad Stripping */
#define MFCO		0x0002	/* Missed Frame Counter Overflow Interrupt */
#define MFCOM		0x0001	/* Missed Frame Counter Overflow Mask */
#define RCVCCO		0x2000	/* Receive Collision Counter Overflow Interrupt */
#define RCVCCOM		0x1000	/* Receive Collision Counter Overflow Mask */
#define TXSTRT		0x0800	/* Transmit Start Status */
#define TXSTRTM		0x0400	/* Transmit Start Mask */
#define JAB		0x0200	/* Jabber Error */
#define JABM		0x0100	/* Jabber Error Mask */


    /*
     *	Bit definitions for CSR15 (Mode Register)
     *
     *	These values are already swap()ed!!
     */

#define PROM		0x0080	/* Promiscuous Mode */
#define DRCVBC		0x0040	/* Disable Receive Broadcast */
#define DRCVPA		0x0020	/* Disable Receive Physical Address */
#define DLNKTST		0x0010	/* Disable Link Status */
#define DAPC		0x0008	/* Disable Automatic Polarity Correction */
#define MENDECL		0x0004	/* MENDEC Loopback Mode */
#define LRTTSEL		0x0002	/* Low Receive Treshold/Transmit Mode Select */
#define PORTSEL1	0x0001	/* Port Select Bits */
#define PORTSEL2	0x8000	/* Port Select Bits */
#define INTL		0x4000	/* Internal Loopback */
#define DRTY		0x2000	/* Disable Retry */
#define FCOLL		0x1000	/* Force Collision */
#define DXMTFCS		0x0800	/* Disable Transmit CRC */
#define LOOP		0x0400	/* Loopback Enable */
#define DTX		0x0200	/* Disable Transmitter */
#define DRX		0x0100	/* Disable Receiver */


    /*
     *	Bit definitions for ISACSR2 (Miscellaneous Configuration)
     *
     *	These values are already swap()ed!!
     */

#define ASEL		0x0200	/* Media Interface Port Auto Select */


    /*
     *	Bit definitions for ISACSR5-7 (LED1-3 Status)
     *
     *	These values are already swap()ed!!
     */

#define LEDOUT		0x0080	/* Current LED Status */
#define PSE		0x8000	/* Pulse Stretcher Enable */
#define XMTE		0x1000	/* Enable Transmit Status Signal */
#define RVPOLE		0x0800	/* Enable Receive Polarity Signal */
#define RCVE		0x0400	/* Enable Receive Status Signal */
#define JABE		0x0200	/* Enable Jabber Signal */
#define COLE		0x0100	/* Enable Collision Signal */


    /*
     *	Receive Descriptor Ring Entry
     */

struct RDRE {
    volatile u_short RMD0;	/* LADR[15:0] */
    volatile u_short RMD1;	/* HADR[23:16] | Receive Flags */
    volatile u_short RMD2;	/* Buffer Byte Count (two's complement) */
    volatile u_short RMD3;	/* Message Byte Count */
};


    /*
     *	Transmit Descriptor Ring Entry
     */

struct TDRE {
    volatile u_short TMD0;	/* LADR[15:0] */
    volatile u_short TMD1;	/* HADR[23:16] | Transmit Flags */
    volatile u_short TMD2;	/* Buffer Byte Count (two's complement) */
    volatile u_short TMD3;	/* Error Flags */
};


    /*
     *	Receive Flags
     */

#define RF_OWN		0x0080	/* PCnet-ISA controller owns the descriptor */
#define RF_ERR		0x0040	/* Error */
#define RF_FRAM		0x0020	/* Framing Error */
#define RF_OFLO		0x0010	/* Overflow Error */
#define RF_CRC		0x0008	/* CRC Error */
#define RF_BUFF		0x0004	/* Buffer Error */
#define RF_STP		0x0002	/* Start of Packet */
#define RF_ENP		0x0001	/* End of Packet */


    /*
     *	Transmit Flags
     */

#define TF_OWN		0x0080	/* PCnet-ISA controller owns the descriptor */
#define TF_ERR		0x0040	/* Error */
#define TF_ADD_FCS	0x0020	/* Controls FCS Generation */
#define TF_MORE		0x0010	/* More than one retry needed */
#define TF_ONE		0x0008	/* One retry needed */
#define TF_DEF		0x0004	/* Deferred */
#define TF_STP		0x0002	/* Start of Packet */
#define TF_ENP		0x0001	/* End of Packet */


    /*
     *	Error Flags
     */

#define EF_BUFF		0x0080	/* Buffer Error */
#define EF_UFLO		0x0040	/* Underflow Error */
#define EF_LCOL		0x0010	/* Late Collision */
#define EF_LCAR		0x0008	/* Loss of Carrier */
#define EF_RTRY		0x0004	/* Retry Error */
#define EF_TDR		0xff03	/* Time Domain Reflectometry */



    /*
     *	MC68230 Parallel Interface/Timer
     */

struct MC68230 {
    volatile u_char PGCR;	/* Port General Control Register */
    u_char Pad1[1];
    volatile u_char PSRR;	/* Port Service Request Register */
    u_char Pad2[1];
    volatile u_char PADDR;	/* Port A Data Direction Register */
    u_char Pad3[1];
    volatile u_char PBDDR;	/* Port B Data Direction Register */
    u_char Pad4[1];
    volatile u_char PCDDR;	/* Port C Data Direction Register */
    u_char Pad5[1];
    volatile u_char PIVR;	/* Port Interrupt Vector Register */
    u_char Pad6[1];
    volatile u_char PACR;	/* Port A Control Register */
    u_char Pad7[1];
    volatile u_char PBCR;	/* Port B Control Register */
    u_char Pad8[1];
    volatile u_char PADR;	/* Port A Data Register */
    u_char Pad9[1];
    volatile u_char PBDR;	/* Port B Data Register */
    u_char Pad10[1];
    volatile u_char PAAR;	/* Port A Alternate Register */
    u_char Pad11[1];
    volatile u_char PBAR;	/* Port B Alternate Register */
    u_char Pad12[1];
    volatile u_char PCDR;	/* Port C Data Register */
    u_char Pad13[1];
    volatile u_char PSR;	/* Port Status Register */
    u_char Pad14[5];
    volatile u_char TCR;	/* Timer Control Register */
    u_char Pad15[1];
    volatile u_char TIVR;	/* Timer Interrupt Vector Register */
    u_char Pad16[3];
    volatile u_char CPRH;	/* Counter Preload Register (High) */
    u_char Pad17[1];
    volatile u_char CPRM;	/* Counter Preload Register (Mid) */
    u_char Pad18[1];
    volatile u_char CPRL;	/* Counter Preload Register (Low) */
    u_char Pad19[3];
    volatile u_char CNTRH;	/* Count Register (High) */
    u_char Pad20[1];
    volatile u_char CNTRM;	/* Count Register (Mid) */
    u_char Pad21[1];
    volatile u_char CNTRL;	/* Count Register (Low) */
    u_char Pad22[1];
    volatile u_char TSR;	/* Timer Status Register */
    u_char Pad23[11];
};


    /*
     *	Ariadne Expansion Board Structure
     */

#define ARIADNE_LANCE		0x360

#define ARIADNE_PIT		0x1000

#define ARIADNE_BOOTPROM	0x4000	/* I guess it's here :-) */
#define ARIADNE_BOOTPROM_SIZE	0x4000

#define ARIADNE_RAM		0x8000	/* Always access WORDs!! */
#define ARIADNE_RAM_SIZE	0x8000