sky2.h

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/*
 * Definitions for the new Marvell Yukon 2 driver.
 */
#ifndef _SKY2_H
#define _SKY2_H

#define ETH_JUMBO_MTU		9000	/* Maximum MTU supported */

/* PCI config registers */
enum {
	PCI_DEV_REG1	= 0x40,
	PCI_DEV_REG2	= 0x44,
	PCI_DEV_STATUS  = 0x7c,
	PCI_DEV_REG3	= 0x80,
	PCI_DEV_REG4	= 0x84,
	PCI_DEV_REG5    = 0x88,
	PCI_CFG_REG_0	= 0x90,
	PCI_CFG_REG_1	= 0x94,
};

/* Yukon-2 */
enum pci_dev_reg_1 {
	PCI_Y2_PIG_ENA	 = 1<<31, /* Enable Plug-in-Go (YUKON-2) */
	PCI_Y2_DLL_DIS	 = 1<<30, /* Disable PCI DLL (YUKON-2) */
	PCI_SW_PWR_ON_RST= 1<<30, /* SW Power on Reset (Yukon-EX) */
	PCI_Y2_PHY2_COMA = 1<<29, /* Set PHY 2 to Coma Mode (YUKON-2) */
	PCI_Y2_PHY1_COMA = 1<<28, /* Set PHY 1 to Coma Mode (YUKON-2) */
	PCI_Y2_PHY2_POWD = 1<<27, /* Set PHY 2 to Power Down (YUKON-2) */
	PCI_Y2_PHY1_POWD = 1<<26, /* Set PHY 1 to Power Down (YUKON-2) */
	PCI_Y2_PME_LEGACY= 1<<15, /* PCI Express legacy power management mode */
};

enum pci_dev_reg_2 {
	PCI_VPD_WR_THR	= 0xffL<<24,	/* Bit 31..24:	VPD Write Threshold */
	PCI_DEV_SEL	= 0x7fL<<17,	/* Bit 23..17:	EEPROM Device Select */
	PCI_VPD_ROM_SZ	= 7L<<14,	/* Bit 16..14:	VPD ROM Size	*/

	PCI_PATCH_DIR	= 0xfL<<8,	/* Bit 11.. 8:	Ext Patches dir 3..0 */
	PCI_EXT_PATCHS	= 0xfL<<4,	/* Bit	7.. 4:	Extended Patches 3..0 */
	PCI_EN_DUMMY_RD	= 1<<3,		/* Enable Dummy Read */
	PCI_REV_DESC	= 1<<2,		/* Reverse Desc. Bytes */

	PCI_USEDATA64	= 1<<0,		/* Use 64Bit Data bus ext */
};

/*	PCI_OUR_REG_4		32 bit	Our Register 4 (Yukon-ECU only) */
enum pci_dev_reg_4 {
					/* (Link Training & Status State Machine) */
	P_TIMER_VALUE_MSK	= 0xffL<<16,	/* Bit 23..16:	Timer Value Mask */
					/* (Active State Power Management) */
	P_FORCE_ASPM_REQUEST	= 1<<15, /* Force ASPM Request (A1 only) */
	P_ASPM_GPHY_LINK_DOWN	= 1<<14, /* GPHY Link Down (A1 only) */
	P_ASPM_INT_FIFO_EMPTY	= 1<<13, /* Internal FIFO Empty (A1 only) */
	P_ASPM_CLKRUN_REQUEST	= 1<<12, /* CLKRUN Request (A1 only) */

	P_ASPM_FORCE_CLKREQ_ENA	= 1<<4,	/* Force CLKREQ Enable (A1b only) */
	P_ASPM_CLKREQ_PAD_CTL	= 1<<3,	/* CLKREQ PAD Control (A1 only) */
	P_ASPM_A1_MODE_SELECT	= 1<<2,	/* A1 Mode Select (A1 only) */
	P_CLK_GATE_PEX_UNIT_ENA	= 1<<1,	/* Enable Gate PEX Unit Clock */
	P_CLK_GATE_ROOT_COR_ENA	= 1<<0,	/* Enable Gate Root Core Clock */
	P_ASPM_CONTROL_MSK	= P_FORCE_ASPM_REQUEST | P_ASPM_GPHY_LINK_DOWN
				  | P_ASPM_CLKRUN_REQUEST | P_ASPM_INT_FIFO_EMPTY,
};

/*	PCI_OUR_REG_5		32 bit	Our Register 5 (Yukon-ECU only) */
enum pci_dev_reg_5 {
					/* Bit 31..27:	for A3 & later */
	P_CTL_DIV_CORE_CLK_ENA	= 1<<31, /* Divide Core Clock Enable */
	P_CTL_SRESET_VMAIN_AV	= 1<<30, /* Soft Reset for Vmain_av De-Glitch */
	P_CTL_BYPASS_VMAIN_AV	= 1<<29, /* Bypass En. for Vmain_av De-Glitch */
	P_CTL_TIM_VMAIN_AV_MSK	= 3<<27, /* Bit 28..27: Timer Vmain_av Mask */
					 /* Bit 26..16: Release Clock on Event */
	P_REL_PCIE_RST_DE_ASS	= 1<<26, /* PCIe Reset De-Asserted */
	P_REL_GPHY_REC_PACKET	= 1<<25, /* GPHY Received Packet */
	P_REL_INT_FIFO_N_EMPTY	= 1<<24, /* Internal FIFO Not Empty */
	P_REL_MAIN_PWR_AVAIL	= 1<<23, /* Main Power Available */
	P_REL_CLKRUN_REQ_REL	= 1<<22, /* CLKRUN Request Release */
	P_REL_PCIE_RESET_ASS	= 1<<21, /* PCIe Reset Asserted */
	P_REL_PME_ASSERTED	= 1<<20, /* PME Asserted */
	P_REL_PCIE_EXIT_L1_ST	= 1<<19, /* PCIe Exit L1 State */
	P_REL_LOADER_NOT_FIN	= 1<<18, /* EPROM Loader Not Finished */
	P_REL_PCIE_RX_EX_IDLE	= 1<<17, /* PCIe Rx Exit Electrical Idle State */
	P_REL_GPHY_LINK_UP	= 1<<16, /* GPHY Link Up */

					/* Bit 10.. 0: Mask for Gate Clock */
	P_GAT_PCIE_RST_ASSERTED	= 1<<10,/* PCIe Reset Asserted */
	P_GAT_GPHY_N_REC_PACKET	= 1<<9, /* GPHY Not Received Packet */
	P_GAT_INT_FIFO_EMPTY	= 1<<8, /* Internal FIFO Empty */
	P_GAT_MAIN_PWR_N_AVAIL	= 1<<7, /* Main Power Not Available */
	P_GAT_CLKRUN_REQ_REL	= 1<<6, /* CLKRUN Not Requested */
	P_GAT_PCIE_RESET_ASS	= 1<<5, /* PCIe Reset Asserted */
	P_GAT_PME_DE_ASSERTED	= 1<<4, /* PME De-Asserted */
	P_GAT_PCIE_ENTER_L1_ST	= 1<<3, /* PCIe Enter L1 State */
	P_GAT_LOADER_FINISHED	= 1<<2, /* EPROM Loader Finished */
	P_GAT_PCIE_RX_EL_IDLE	= 1<<1, /* PCIe Rx Electrical Idle State */
	P_GAT_GPHY_LINK_DOWN	= 1<<0,	/* GPHY Link Down */

	PCIE_OUR5_EVENT_CLK_D3_SET = P_REL_GPHY_REC_PACKET |
				     P_REL_INT_FIFO_N_EMPTY |
				     P_REL_PCIE_EXIT_L1_ST |
				     P_REL_PCIE_RX_EX_IDLE |
				     P_GAT_GPHY_N_REC_PACKET |
				     P_GAT_INT_FIFO_EMPTY |
				     P_GAT_PCIE_ENTER_L1_ST |
				     P_GAT_PCIE_RX_EL_IDLE,
};

#/*	PCI_CFG_REG_1			32 bit	Config Register 1 (Yukon-Ext only) */
enum pci_cfg_reg1 {
	P_CF1_DIS_REL_EVT_RST	= 1<<24, /* Dis. Rel. Event during PCIE reset */
										/* Bit 23..21: Release Clock on Event */
	P_CF1_REL_LDR_NOT_FIN	= 1<<23, /* EEPROM Loader Not Finished */
	P_CF1_REL_VMAIN_AVLBL	= 1<<22, /* Vmain available */
	P_CF1_REL_PCIE_RESET	= 1<<21, /* PCI-E reset */
										/* Bit 20..18: Gate Clock on Event */
	P_CF1_GAT_LDR_NOT_FIN	= 1<<20, /* EEPROM Loader Finished */
	P_CF1_GAT_PCIE_RX_IDLE	= 1<<19, /* PCI-E Rx Electrical idle */
	P_CF1_GAT_PCIE_RESET	= 1<<18, /* PCI-E Reset */
	P_CF1_PRST_PHY_CLKREQ	= 1<<17, /* Enable PCI-E rst & PM2PHY gen. CLKREQ */
	P_CF1_PCIE_RST_CLKREQ	= 1<<16, /* Enable PCI-E rst generate CLKREQ */

	P_CF1_ENA_CFG_LDR_DONE	= 1<<8, /* Enable core level Config loader done */

	P_CF1_ENA_TXBMU_RD_IDLE	= 1<<1, /* Enable TX BMU Read  IDLE for ASPM */
	P_CF1_ENA_TXBMU_WR_IDLE	= 1<<0, /* Enable TX BMU Write IDLE for ASPM */

	PCIE_CFG1_EVENT_CLK_D3_SET = P_CF1_DIS_REL_EVT_RST |
					P_CF1_REL_LDR_NOT_FIN |
					P_CF1_REL_VMAIN_AVLBL |
					P_CF1_REL_PCIE_RESET |
					P_CF1_GAT_LDR_NOT_FIN |
					P_CF1_GAT_PCIE_RESET |
					P_CF1_PRST_PHY_CLKREQ |
					P_CF1_ENA_CFG_LDR_DONE |
					P_CF1_ENA_TXBMU_RD_IDLE |
					P_CF1_ENA_TXBMU_WR_IDLE,
};


#define PCI_STATUS_ERROR_BITS (PCI_STATUS_DETECTED_PARITY | \
			       PCI_STATUS_SIG_SYSTEM_ERROR | \
			       PCI_STATUS_REC_MASTER_ABORT | \
			       PCI_STATUS_REC_TARGET_ABORT | \
			       PCI_STATUS_PARITY)

enum csr_regs {
	B0_RAP		= 0x0000,
	B0_CTST		= 0x0004,
	B0_Y2LED	= 0x0005,
	B0_POWER_CTRL	= 0x0007,
	B0_ISRC		= 0x0008,
	B0_IMSK		= 0x000c,
	B0_HWE_ISRC	= 0x0010,
	B0_HWE_IMSK	= 0x0014,

	/* Special ISR registers (Yukon-2 only) */
	B0_Y2_SP_ISRC2	= 0x001c,
	B0_Y2_SP_ISRC3	= 0x0020,
	B0_Y2_SP_EISR	= 0x0024,
	B0_Y2_SP_LISR	= 0x0028,
	B0_Y2_SP_ICR	= 0x002c,

	B2_MAC_1	= 0x0100,
	B2_MAC_2	= 0x0108,
	B2_MAC_3	= 0x0110,
	B2_CONN_TYP	= 0x0118,
	B2_PMD_TYP	= 0x0119,
	B2_MAC_CFG	= 0x011a,
	B2_CHIP_ID	= 0x011b,
	B2_E_0		= 0x011c,

	B2_Y2_CLK_GATE  = 0x011d,
	B2_Y2_HW_RES	= 0x011e,
	B2_E_3		= 0x011f,
	B2_Y2_CLK_CTRL	= 0x0120,

	B2_TI_INI	= 0x0130,
	B2_TI_VAL	= 0x0134,
	B2_TI_CTRL	= 0x0138,
	B2_TI_TEST	= 0x0139,

	B2_TST_CTRL1	= 0x0158,
	B2_TST_CTRL2	= 0x0159,
	B2_GP_IO	= 0x015c,

	B2_I2C_CTRL	= 0x0160,
	B2_I2C_DATA	= 0x0164,
	B2_I2C_IRQ	= 0x0168,
	B2_I2C_SW	= 0x016c,

	B3_RAM_ADDR	= 0x0180,
	B3_RAM_DATA_LO	= 0x0184,
	B3_RAM_DATA_HI	= 0x0188,

/* RAM Interface Registers */
/* Yukon-2: use RAM_BUFFER() to access the RAM buffer */
/*
 * The HW-Spec. calls this registers Timeout Value 0..11. But this names are
 * not usable in SW. Please notice these are NOT real timeouts, these are
 * the number of qWords transferred continuously.
 */
#define RAM_BUFFER(port, reg)	(reg | (port <<6))

	B3_RI_WTO_R1	= 0x0190,
	B3_RI_WTO_XA1	= 0x0191,
	B3_RI_WTO_XS1	= 0x0192,
	B3_RI_RTO_R1	= 0x0193,
	B3_RI_RTO_XA1	= 0x0194,
	B3_RI_RTO_XS1	= 0x0195,
	B3_RI_WTO_R2	= 0x0196,
	B3_RI_WTO_XA2	= 0x0197,
	B3_RI_WTO_XS2	= 0x0198,
	B3_RI_RTO_R2	= 0x0199,
	B3_RI_RTO_XA2	= 0x019a,
	B3_RI_RTO_XS2	= 0x019b,
	B3_RI_TO_VAL	= 0x019c,
	B3_RI_CTRL	= 0x01a0,
	B3_RI_TEST	= 0x01a2,
	B3_MA_TOINI_RX1	= 0x01b0,
	B3_MA_TOINI_RX2	= 0x01b1,
	B3_MA_TOINI_TX1	= 0x01b2,
	B3_MA_TOINI_TX2	= 0x01b3,
	B3_MA_TOVAL_RX1	= 0x01b4,
	B3_MA_TOVAL_RX2	= 0x01b5,
	B3_MA_TOVAL_TX1	= 0x01b6,
	B3_MA_TOVAL_TX2	= 0x01b7,
	B3_MA_TO_CTRL	= 0x01b8,
	B3_MA_TO_TEST	= 0x01ba,
	B3_MA_RCINI_RX1	= 0x01c0,
	B3_MA_RCINI_RX2	= 0x01c1,
	B3_MA_RCINI_TX1	= 0x01c2,
	B3_MA_RCINI_TX2	= 0x01c3,
	B3_MA_RCVAL_RX1	= 0x01c4,
	B3_MA_RCVAL_RX2	= 0x01c5,
	B3_MA_RCVAL_TX1	= 0x01c6,
	B3_MA_RCVAL_TX2	= 0x01c7,
	B3_MA_RC_CTRL	= 0x01c8,
	B3_MA_RC_TEST	= 0x01ca,
	B3_PA_TOINI_RX1	= 0x01d0,
	B3_PA_TOINI_RX2	= 0x01d4,
	B3_PA_TOINI_TX1	= 0x01d8,
	B3_PA_TOINI_TX2	= 0x01dc,
	B3_PA_TOVAL_RX1	= 0x01e0,
	B3_PA_TOVAL_RX2	= 0x01e4,
	B3_PA_TOVAL_TX1	= 0x01e8,
	B3_PA_TOVAL_TX2	= 0x01ec,
	B3_PA_CTRL	= 0x01f0,
	B3_PA_TEST	= 0x01f2,

	Y2_CFG_SPC	= 0x1c00,	/* PCI config space region */
	Y2_CFG_AER      = 0x1d00,	/* PCI Advanced Error Report region */
};

/*	B0_CTST			16 bit	Control/Status register */
enum {
	Y2_VMAIN_AVAIL	= 1<<17,/* VMAIN available (YUKON-2 only) */
	Y2_VAUX_AVAIL	= 1<<16,/* VAUX available (YUKON-2 only) */
	Y2_HW_WOL_ON	= 1<<15,/* HW WOL On  (Yukon-EC Ultra A1 only) */
	Y2_HW_WOL_OFF	= 1<<14,/* HW WOL On  (Yukon-EC Ultra A1 only) */
	Y2_ASF_ENABLE	= 1<<13,/* ASF Unit Enable (YUKON-2 only) */
	Y2_ASF_DISABLE	= 1<<12,/* ASF Unit Disable (YUKON-2 only) */
	Y2_CLK_RUN_ENA	= 1<<11,/* CLK_RUN Enable  (YUKON-2 only) */
	Y2_CLK_RUN_DIS	= 1<<10,/* CLK_RUN Disable (YUKON-2 only) */
	Y2_LED_STAT_ON	= 1<<9, /* Status LED On  (YUKON-2 only) */
	Y2_LED_STAT_OFF	= 1<<8, /* Status LED Off (YUKON-2 only) */

	CS_ST_SW_IRQ	= 1<<7,	/* Set IRQ SW Request */
	CS_CL_SW_IRQ	= 1<<6,	/* Clear IRQ SW Request */
	CS_STOP_DONE	= 1<<5,	/* Stop Master is finished */
	CS_STOP_MAST	= 1<<4,	/* Command Bit to stop the master */
	CS_MRST_CLR	= 1<<3,	/* Clear Master reset	*/
	CS_MRST_SET	= 1<<2,	/* Set Master reset	*/
	CS_RST_CLR	= 1<<1,	/* Clear Software reset	*/
	CS_RST_SET	= 1,	/* Set   Software reset	*/
};

/*	B0_LED			 8 Bit	LED register */
enum {
/* Bit  7.. 2:	reserved */
	LED_STAT_ON	= 1<<1,	/* Status LED on	*/
	LED_STAT_OFF	= 1,	/* Status LED off	*/
};

/*	B0_POWER_CTRL	 8 Bit	Power Control reg (YUKON only) */
enum {
	PC_VAUX_ENA	= 1<<7,	/* Switch VAUX Enable  */
	PC_VAUX_DIS	= 1<<6,	/* Switch VAUX Disable */
	PC_VCC_ENA	= 1<<5,	/* Switch VCC Enable  */
	PC_VCC_DIS	= 1<<4,	/* Switch VCC Disable */
	PC_VAUX_ON	= 1<<3,	/* Switch VAUX On  */
	PC_VAUX_OFF	= 1<<2,	/* Switch VAUX Off */
	PC_VCC_ON	= 1<<1,	/* Switch VCC On  */
	PC_VCC_OFF	= 1<<0,	/* Switch VCC Off */
};

/*	B2_IRQM_MSK 	32 bit	IRQ Moderation Mask */

/*	B0_Y2_SP_ISRC2	32 bit	Special Interrupt Source Reg 2 */
/*	B0_Y2_SP_ISRC3	32 bit	Special Interrupt Source Reg 3 */
/*	B0_Y2_SP_EISR	32 bit	Enter ISR Reg */
/*	B0_Y2_SP_LISR	32 bit	Leave ISR Reg */
enum {
	Y2_IS_HW_ERR	= 1<<31,	/* Interrupt HW Error */
	Y2_IS_STAT_BMU	= 1<<30,	/* Status BMU Interrupt */
	Y2_IS_ASF	= 1<<29,	/* ASF subsystem Interrupt */

	Y2_IS_POLL_CHK	= 1<<27,	/* Check IRQ from polling unit */
	Y2_IS_TWSI_RDY	= 1<<26,	/* IRQ on end of TWSI Tx */
	Y2_IS_IRQ_SW	= 1<<25,	/* SW forced IRQ	*/
	Y2_IS_TIMINT	= 1<<24,	/* IRQ from Timer	*/

	Y2_IS_IRQ_PHY2	= 1<<12,	/* Interrupt from PHY 2 */
	Y2_IS_IRQ_MAC2	= 1<<11,	/* Interrupt from MAC 2 */
	Y2_IS_CHK_RX2	= 1<<10,	/* Descriptor error Rx 2 */
	Y2_IS_CHK_TXS2	= 1<<9,		/* Descriptor error TXS 2 */
	Y2_IS_CHK_TXA2	= 1<<8,		/* Descriptor error TXA 2 */

	Y2_IS_IRQ_PHY1	= 1<<4,		/* Interrupt from PHY 1 */
	Y2_IS_IRQ_MAC1	= 1<<3,		/* Interrupt from MAC 1 */
	Y2_IS_CHK_RX1	= 1<<2,		/* Descriptor error Rx 1 */
	Y2_IS_CHK_TXS1	= 1<<1,		/* Descriptor error TXS 1 */
	Y2_IS_CHK_TXA1	= 1<<0,		/* Descriptor error TXA 1 */

	Y2_IS_BASE	= Y2_IS_HW_ERR | Y2_IS_STAT_BMU,
	Y2_IS_PORT_1	= Y2_IS_IRQ_PHY1 | Y2_IS_IRQ_MAC1
		          | Y2_IS_CHK_TXA1 | Y2_IS_CHK_RX1,