cassini.h
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/* $Id: cassini.h,v 1.16 2004/08/17 21:15:16 zaumen Exp $ * cassini.h: Definitions for Sun Microsystems Cassini(+) ethernet driver. * * Copyright (C) 2004 Sun Microsystems Inc. * Copyright (c) 2003 Adrian Sun (asun@darksunrising.com) * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of the * License, or (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA * 02111-1307, USA. * * vendor id: 0x108E (Sun Microsystems, Inc.) * device id: 0xabba (Cassini) * revision ids: 0x01 = Cassini * 0x02 = Cassini rev 2 * 0x10 = Cassini+ * 0x11 = Cassini+ 0.2u * * vendor id: 0x100b (National Semiconductor) * device id: 0x0035 (DP83065/Saturn) * revision ids: 0x30 = Saturn B2 * * rings are all offset from 0. * * there are two clock domains: * PCI: 33/66MHz clock * chip: 125MHz clock */#ifndef _CASSINI_H#define _CASSINI_H/* cassini register map: 2M memory mapped in 32-bit memory space accessible as * 32-bit words. there is no i/o port access. REG_ addresses are * shared between cassini and cassini+. REG_PLUS_ addresses only * appear in cassini+. REG_MINUS_ addresses only appear in cassini. */#define CAS_ID_REV2 0x02#define CAS_ID_REVPLUS 0x10#define CAS_ID_REVPLUS02u 0x11#define CAS_ID_REVSATURNB2 0x30/** global resources **//* this register sets the weights for the weighted round robin arbiter. e.g., * if rx weight == 1 and tx weight == 0, rx == 2x tx transfer credit * for its next turn to access the pci bus. * map: 0x0 = x1, 0x1 = x2, 0x2 = x4, 0x3 = x8 * DEFAULT: 0x0, SIZE: 5 bits */#define REG_CAWR 0x0004 /* core arbitration weight */#define CAWR_RX_DMA_WEIGHT_SHIFT 0#define CAWR_RX_DMA_WEIGHT_MASK 0x03 /* [0:1] */#define CAWR_TX_DMA_WEIGHT_SHIFT 2#define CAWR_TX_DMA_WEIGHT_MASK 0x0C /* [3:2] */#define CAWR_RR_DIS 0x10 /* [4] *//* if enabled, BIM can send bursts across PCI bus > cacheline size. burst * sizes determined by length of packet or descriptor transfer and the * max length allowed by the target. * DEFAULT: 0x0, SIZE: 1 bit */#define REG_INF_BURST 0x0008 /* infinite burst enable reg */#define INF_BURST_EN 0x1 /* enable *//* top level interrupts [0-9] are auto-cleared to 0 when the status * register is read. second level interrupts [13 - 18] are cleared at * the source. tx completion register 3 is replicated in [19 - 31] * DEFAULT: 0x00000000, SIZE: 29 bits */#define REG_INTR_STATUS 0x000C /* interrupt status register */#define INTR_TX_INTME 0x00000001 /* frame w/ INT ME desc bit set xferred from host queue to TX FIFO */#define INTR_TX_ALL 0x00000002 /* all xmit frames xferred into TX FIFO. i.e., TX Kick == TX complete. if PACED_MODE set, then TX FIFO also empty */#define INTR_TX_DONE 0x00000004 /* any frame xferred into tx FIFO */#define INTR_TX_TAG_ERROR 0x00000008 /* TX FIFO tag framing corrupted. FATAL ERROR */#define INTR_RX_DONE 0x00000010 /* at least 1 frame xferred from RX FIFO to host mem. RX completion reg updated. may be delayed by recv intr blanking. */#define INTR_RX_BUF_UNAVAIL 0x00000020 /* no more receive buffers. RX Kick == RX complete */#define INTR_RX_TAG_ERROR 0x00000040 /* RX FIFO tag framing corrupted. FATAL ERROR */#define INTR_RX_COMP_FULL 0x00000080 /* no more room in completion ring to post descriptors. RX complete head incr to almost reach RX complete tail */#define INTR_RX_BUF_AE 0x00000100 /* less than the programmable threshold # of free descr avail for hw use */#define INTR_RX_COMP_AF 0x00000200 /* less than the programmable threshold # of descr spaces for hw use in completion descr ring */#define INTR_RX_LEN_MISMATCH 0x00000400 /* len field from MAC != len of non-reassembly pkt from fifo during DMA or header parser provides TCP header and payload size > MAC packet size. FATAL ERROR */#define INTR_SUMMARY 0x00001000 /* summary interrupt bit. this bit will be set if an interrupt generated on the pci bus. useful when driver is polling for interrupts */#define INTR_PCS_STATUS 0x00002000 /* PCS interrupt status register */#define INTR_TX_MAC_STATUS 0x00004000 /* TX MAC status register has at least 1 unmasked interrupt set */#define INTR_RX_MAC_STATUS 0x00008000 /* RX MAC status register has at least 1 unmasked interrupt set */#define INTR_MAC_CTRL_STATUS 0x00010000 /* MAC control status register has at least 1 unmasked interrupt set */#define INTR_MIF_STATUS 0x00020000 /* MIF status register has at least 1 unmasked interrupt set */#define INTR_PCI_ERROR_STATUS 0x00040000 /* PCI error status register in the BIF has at least 1 unmasked interrupt set */#define INTR_TX_COMP_3_MASK 0xFFF80000 /* mask for TX completion 3 reg data */#define INTR_TX_COMP_3_SHIFT 19#define INTR_ERROR_MASK (INTR_MIF_STATUS | INTR_PCI_ERROR_STATUS | \ INTR_PCS_STATUS | INTR_RX_LEN_MISMATCH | \ INTR_TX_MAC_STATUS | INTR_RX_MAC_STATUS | \ INTR_TX_TAG_ERROR | INTR_RX_TAG_ERROR | \ INTR_MAC_CTRL_STATUS)/* determines which status events will cause an interrupt. layout same * as REG_INTR_STATUS. * DEFAULT: 0xFFFFFFFF, SIZE: 16 bits */#define REG_INTR_MASK 0x0010 /* Interrupt mask *//* top level interrupt bits that are cleared during read of REG_INTR_STATUS_ALIAS. * useful when driver is polling for interrupts. layout same as REG_INTR_MASK. * DEFAULT: 0x00000000, SIZE: 12 bits */#define REG_ALIAS_CLEAR 0x0014 /* alias clear mask (used w/ status alias) *//* same as REG_INTR_STATUS except that only bits cleared are those selected by * REG_ALIAS_CLEAR * DEFAULT: 0x00000000, SIZE: 29 bits */#define REG_INTR_STATUS_ALIAS 0x001C /* interrupt status alias (selective clear) *//* DEFAULT: 0x0, SIZE: 3 bits */#define REG_PCI_ERR_STATUS 0x1000 /* PCI error status */#define PCI_ERR_BADACK 0x01 /* reserved in Cassini+. set if no ACK64# during ABS64 cycle in Cassini. */#define PCI_ERR_DTRTO 0x02 /* delayed xaction timeout. set if no read retry after 2^15 clocks */#define PCI_ERR_OTHER 0x04 /* other PCI errors */#define PCI_ERR_BIM_DMA_WRITE 0x08 /* BIM received 0 count DMA write req. unused in Cassini. */#define PCI_ERR_BIM_DMA_READ 0x10 /* BIM received 0 count DMA read req. unused in Cassini. */#define PCI_ERR_BIM_DMA_TIMEOUT 0x20 /* BIM received 255 retries during DMA. unused in cassini. *//* mask for PCI status events that will set PCI_ERR_STATUS. if cleared, event * causes an interrupt to be generated. * DEFAULT: 0x7, SIZE: 3 bits */#define REG_PCI_ERR_STATUS_MASK 0x1004 /* PCI Error status mask *//* used to configure PCI related parameters that are not in PCI config space. * DEFAULT: 0bxx000, SIZE: 5 bits */#define REG_BIM_CFG 0x1008 /* BIM Configuration */#define BIM_CFG_RESERVED0 0x001 /* reserved */#define BIM_CFG_RESERVED1 0x002 /* reserved */#define BIM_CFG_64BIT_DISABLE 0x004 /* disable 64-bit mode */#define BIM_CFG_66MHZ 0x008 /* (ro) 1 = 66MHz, 0 = < 66MHz */#define BIM_CFG_32BIT 0x010 /* (ro) 1 = 32-bit slot, 0 = 64-bit */#define BIM_CFG_DPAR_INTR_ENABLE 0x020 /* detected parity err enable */#define BIM_CFG_RMA_INTR_ENABLE 0x040 /* master abort intr enable */#define BIM_CFG_RTA_INTR_ENABLE 0x080 /* target abort intr enable */#define BIM_CFG_RESERVED2 0x100 /* reserved */#define BIM_CFG_BIM_DISABLE 0x200 /* stop BIM DMA. use before global reset. reserved in Cassini. */#define BIM_CFG_BIM_STATUS 0x400 /* (ro) 1 = BIM DMA suspended. reserved in Cassini. */#define BIM_CFG_PERROR_BLOCK 0x800 /* block PERR# to pci bus. def: 0. reserved in Cassini. *//* DEFAULT: 0x00000000, SIZE: 32 bits */#define REG_BIM_DIAG 0x100C /* BIM Diagnostic */#define BIM_DIAG_MSTR_SM_MASK 0x3FFFFF00 /* PCI master controller state machine bits [21:0] */#define BIM_DIAG_BRST_SM_MASK 0x7F /* PCI burst controller state machine bits [6:0] *//* writing to SW_RESET_TX and SW_RESET_RX will issue a global * reset. poll until TX and RX read back as 0's for completion. */#define REG_SW_RESET 0x1010 /* Software reset */#define SW_RESET_TX 0x00000001 /* reset TX DMA engine. poll until cleared to 0. */#define SW_RESET_RX 0x00000002 /* reset RX DMA engine. poll until cleared to 0. */#define SW_RESET_RSTOUT 0x00000004 /* force RSTOUT# pin active (low). resets PHY and anything else connected to RSTOUT#. RSTOUT# is also activated by local PCI reset when hot-swap is being done. */#define SW_RESET_BLOCK_PCS_SLINK 0x00000008 /* if a global reset is done with this bit set, PCS and SLINK modules won't be reset. i.e., link won't drop. */#define SW_RESET_BREQ_SM_MASK 0x00007F00 /* breq state machine [6:0] */#define SW_RESET_PCIARB_SM_MASK 0x00070000 /* pci arbitration state bits: 0b000: ARB_IDLE1 0b001: ARB_IDLE2 0b010: ARB_WB_ACK 0b011: ARB_WB_WAT 0b100: ARB_RB_ACK 0b101: ARB_RB_WAT 0b110: ARB_RB_END 0b111: ARB_WB_END */#define SW_RESET_RDPCI_SM_MASK 0x00300000 /* read pci state bits: 0b00: RD_PCI_WAT 0b01: RD_PCI_RDY 0b11: RD_PCI_ACK */#define SW_RESET_RDARB_SM_MASK 0x00C00000 /* read arbitration state bits: 0b00: AD_IDL_RX 0b01: AD_ACK_RX 0b10: AD_ACK_TX 0b11: AD_IDL_TX */#define SW_RESET_WRPCI_SM_MASK 0x06000000 /* write pci state bits 0b00: WR_PCI_WAT 0b01: WR_PCI_RDY 0b11: WR_PCI_ACK */#define SW_RESET_WRARB_SM_MASK 0x38000000 /* write arbitration state bits: 0b000: ARB_IDLE1 0b001: ARB_IDLE2 0b010: ARB_TX_ACK 0b011: ARB_TX_WAT 0b100: ARB_RX_ACK 0b110: ARB_RX_WAT *//* Cassini only. 64-bit register used to check PCI datapath. when read, * value written has both lower and upper 32-bit halves rotated to the right * one bit position. e.g., FFFFFFFF FFFFFFFF -> 7FFFFFFF 7FFFFFFF */#define REG_MINUS_BIM_DATAPATH_TEST 0x1018 /* Cassini: BIM datapath test Cassini+: reserved *//* output enables are provided for each device's chip select and for the rest * of the outputs from cassini to its local bus devices. two sw programmable * bits are connected to general purpus control/status bits. * DEFAULT: 0x7 */#define REG_BIM_LOCAL_DEV_EN 0x1020 /* BIM local device output EN. default: 0x7 */#define BIM_LOCAL_DEV_PAD 0x01 /* address bus, RW signal, and OE signal output enable on the local bus interface. these are shared between both local bus devices. tristate when 0. */⌨️ 快捷键说明
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