📄 via-velocity.h
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#define RXESR_RDSTR 0x01/* * Bits in the ISR register */#define ISR_ISR3 0x80000000UL#define ISR_ISR2 0x40000000UL#define ISR_ISR1 0x20000000UL#define ISR_ISR0 0x10000000UL#define ISR_TXSTLI 0x02000000UL#define ISR_RXSTLI 0x01000000UL#define ISR_HFLD 0x00800000UL#define ISR_UDPI 0x00400000UL#define ISR_MIBFI 0x00200000UL#define ISR_SHDNI 0x00100000UL#define ISR_PHYI 0x00080000UL#define ISR_PWEI 0x00040000UL#define ISR_TMR1I 0x00020000UL#define ISR_TMR0I 0x00010000UL#define ISR_SRCI 0x00008000UL#define ISR_LSTPEI 0x00004000UL#define ISR_LSTEI 0x00002000UL#define ISR_OVFI 0x00001000UL#define ISR_FLONI 0x00000800UL#define ISR_RACEI 0x00000400UL#define ISR_TXWB1I 0x00000200UL#define ISR_TXWB0I 0x00000100UL#define ISR_PTX3I 0x00000080UL#define ISR_PTX2I 0x00000040UL#define ISR_PTX1I 0x00000020UL#define ISR_PTX0I 0x00000010UL#define ISR_PTXI 0x00000008UL#define ISR_PRXI 0x00000004UL#define ISR_PPTXI 0x00000002UL#define ISR_PPRXI 0x00000001UL/* * Bits in the IMR register */#define IMR_TXSTLM 0x02000000UL#define IMR_UDPIM 0x00400000UL#define IMR_MIBFIM 0x00200000UL#define IMR_SHDNIM 0x00100000UL#define IMR_PHYIM 0x00080000UL#define IMR_PWEIM 0x00040000UL#define IMR_TMR1IM 0x00020000UL#define IMR_TMR0IM 0x00010000UL#define IMR_SRCIM 0x00008000UL#define IMR_LSTPEIM 0x00004000UL#define IMR_LSTEIM 0x00002000UL#define IMR_OVFIM 0x00001000UL#define IMR_FLONIM 0x00000800UL#define IMR_RACEIM 0x00000400UL#define IMR_TXWB1IM 0x00000200UL#define IMR_TXWB0IM 0x00000100UL#define IMR_PTX3IM 0x00000080UL#define IMR_PTX2IM 0x00000040UL#define IMR_PTX1IM 0x00000020UL#define IMR_PTX0IM 0x00000010UL#define IMR_PTXIM 0x00000008UL#define IMR_PRXIM 0x00000004UL#define IMR_PPTXIM 0x00000002UL#define IMR_PPRXIM 0x00000001UL/* 0x0013FB0FUL = initial value of IMR */#define INT_MASK_DEF (IMR_PPTXIM|IMR_PPRXIM|IMR_PTXIM|IMR_PRXIM|\ IMR_PWEIM|IMR_TXWB0IM|IMR_TXWB1IM|IMR_FLONIM|\ IMR_OVFIM|IMR_LSTEIM|IMR_LSTPEIM|IMR_SRCIM|IMR_MIBFIM|\ IMR_SHDNIM|IMR_TMR1IM|IMR_TMR0IM|IMR_TXSTLM)/* * Bits in the TDCSR0/1, RDCSR0 register */#define TRDCSR_DEAD 0x0008#define TRDCSR_WAK 0x0004#define TRDCSR_ACT 0x0002#define TRDCSR_RUN 0x0001/* * Bits in the CAMADDR register */#define CAMADDR_CAMEN 0x80#define CAMADDR_VCAMSL 0x40/* * Bits in the CAMCR register */#define CAMCR_PS1 0x80#define CAMCR_PS0 0x40#define CAMCR_AITRPKT 0x20#define CAMCR_AITR16 0x10#define CAMCR_CAMRD 0x08#define CAMCR_CAMWR 0x04#define CAMCR_PS_CAM_MASK 0x40#define CAMCR_PS_CAM_DATA 0x80#define CAMCR_PS_MAR 0x00/* * Bits in the MIICFG register */#define MIICFG_MPO1 0x80#define MIICFG_MPO0 0x40#define MIICFG_MFDC 0x20/* * Bits in the MIISR register */#define MIISR_MIDLE 0x80/* * Bits in the PHYSR0 register */#define PHYSR0_PHYRST 0x80#define PHYSR0_LINKGD 0x40#define PHYSR0_FDPX 0x10#define PHYSR0_SPDG 0x08#define PHYSR0_SPD10 0x04#define PHYSR0_RXFLC 0x02#define PHYSR0_TXFLC 0x01/* * Bits in the PHYSR1 register */#define PHYSR1_PHYTBI 0x01/* * Bits in the MIICR register */#define MIICR_MAUTO 0x80#define MIICR_RCMD 0x40#define MIICR_WCMD 0x20#define MIICR_MDPM 0x10#define MIICR_MOUT 0x08#define MIICR_MDO 0x04#define MIICR_MDI 0x02#define MIICR_MDC 0x01/* * Bits in the MIIADR register */#define MIIADR_SWMPL 0x80/* * Bits in the CFGA register */#define CFGA_PMHCTG 0x08#define CFGA_GPIO1PD 0x04#define CFGA_ABSHDN 0x02#define CFGA_PACPI 0x01/* * Bits in the CFGB register */#define CFGB_GTCKOPT 0x80#define CFGB_MIIOPT 0x40#define CFGB_CRSEOPT 0x20#define CFGB_OFSET 0x10#define CFGB_CRANDOM 0x08#define CFGB_CAP 0x04#define CFGB_MBA 0x02#define CFGB_BAKOPT 0x01/* * Bits in the CFGC register */#define CFGC_EELOAD 0x80#define CFGC_BROPT 0x40#define CFGC_DLYEN 0x20#define CFGC_DTSEL 0x10#define CFGC_BTSEL 0x08#define CFGC_BPS2 0x04 /* bootrom select[2] */#define CFGC_BPS1 0x02 /* bootrom select[1] */#define CFGC_BPS0 0x01 /* bootrom select[0] *//* * Bits in the CFGD register */#define CFGD_IODIS 0x80#define CFGD_MSLVDACEN 0x40#define CFGD_CFGDACEN 0x20#define CFGD_PCI64EN 0x10#define CFGD_HTMRL4 0x08/* * Bits in the DCFG1 register */#define DCFG_XMWI 0x8000#define DCFG_XMRM 0x4000#define DCFG_XMRL 0x2000#define DCFG_PERDIS 0x1000#define DCFG_MRWAIT 0x0400#define DCFG_MWWAIT 0x0200#define DCFG_LATMEN 0x0100/* * Bits in the MCFG0 register */#define MCFG_RXARB 0x0080#define MCFG_RFT1 0x0020#define MCFG_RFT0 0x0010#define MCFG_LOWTHOPT 0x0008#define MCFG_PQEN 0x0004#define MCFG_RTGOPT 0x0002#define MCFG_VIDFR 0x0001/* * Bits in the MCFG1 register */#define MCFG_TXARB 0x8000#define MCFG_TXQBK1 0x0800#define MCFG_TXQBK0 0x0400#define MCFG_TXQNOBK 0x0200#define MCFG_SNAPOPT 0x0100/* * Bits in the PMCC register */#define PMCC_DSI 0x80#define PMCC_D2_DIS 0x40#define PMCC_D1_DIS 0x20#define PMCC_D3C_EN 0x10#define PMCC_D3H_EN 0x08#define PMCC_D2_EN 0x04#define PMCC_D1_EN 0x02#define PMCC_D0_EN 0x01/* * Bits in STICKHW */#define STICKHW_SWPTAG 0x10#define STICKHW_WOLSR 0x08#define STICKHW_WOLEN 0x04#define STICKHW_DS1 0x02 /* R/W by software/cfg cycle */#define STICKHW_DS0 0x01 /* suspend well DS write port *//* * Bits in the MIBCR register */#define MIBCR_MIBISTOK 0x80#define MIBCR_MIBISTGO 0x40#define MIBCR_MIBINC 0x20#define MIBCR_MIBHI 0x10#define MIBCR_MIBFRZ 0x08#define MIBCR_MIBFLSH 0x04#define MIBCR_MPTRINI 0x02#define MIBCR_MIBCLR 0x01/* * Bits in the EERSV register */#define EERSV_BOOT_RPL ((u8) 0x01) /* Boot method selection for VT6110 */#define EERSV_BOOT_MASK ((u8) 0x06)#define EERSV_BOOT_INT19 ((u8) 0x00)#define EERSV_BOOT_INT18 ((u8) 0x02)#define EERSV_BOOT_LOCAL ((u8) 0x04)#define EERSV_BOOT_BEV ((u8) 0x06)/* * Bits in BPCMD */#define BPCMD_BPDNE 0x80#define BPCMD_EBPWR 0x02#define BPCMD_EBPRD 0x01/* * Bits in the EECSR register */#define EECSR_EMBP 0x40 /* eeprom embeded programming */#define EECSR_RELOAD 0x20 /* eeprom content reload */#define EECSR_DPM 0x10 /* eeprom direct programming */#define EECSR_ECS 0x08 /* eeprom CS pin */#define EECSR_ECK 0x04 /* eeprom CK pin */#define EECSR_EDI 0x02 /* eeprom DI pin */#define EECSR_EDO 0x01 /* eeprom DO pin *//* * Bits in the EMBCMD register */#define EMBCMD_EDONE 0x80#define EMBCMD_EWDIS 0x08#define EMBCMD_EWEN 0x04#define EMBCMD_EWR 0x02#define EMBCMD_ERD 0x01/* * Bits in TESTCFG register */#define TESTCFG_HBDIS 0x80/* * Bits in CHIPGCR register */#define CHIPGCR_FCGMII 0x80#define CHIPGCR_FCFDX 0x40#define CHIPGCR_FCRESV 0x20#define CHIPGCR_FCMODE 0x10#define CHIPGCR_LPSOPT 0x08#define CHIPGCR_TM1US 0x04#define CHIPGCR_TM0US 0x02#define CHIPGCR_PHYINTEN 0x01/* * Bits in WOLCR0 */#define WOLCR_MSWOLEN7 0x0080 /* enable pattern match filtering */#define WOLCR_MSWOLEN6 0x0040#define WOLCR_MSWOLEN5 0x0020#define WOLCR_MSWOLEN4 0x0010#define WOLCR_MSWOLEN3 0x0008#define WOLCR_MSWOLEN2 0x0004#define WOLCR_MSWOLEN1 0x0002#define WOLCR_MSWOLEN0 0x0001#define WOLCR_ARP_EN 0x0001/* * Bits in WOLCR1 */#define WOLCR_LINKOFF_EN 0x0800 /* link off detected enable */#define WOLCR_LINKON_EN 0x0400 /* link on detected enable */#define WOLCR_MAGIC_EN 0x0200 /* magic packet filter enable */#define WOLCR_UNICAST_EN 0x0100 /* unicast filter enable *//* * Bits in PWCFG */#define PWCFG_PHYPWOPT 0x80 /* internal MII I/F timing */#define PWCFG_PCISTICK 0x40 /* PCI sticky R/W enable */#define PWCFG_WOLTYPE 0x20 /* pulse(1) or button (0) */#define PWCFG_LEGCY_WOL 0x10#define PWCFG_PMCSR_PME_SR 0x08#define PWCFG_PMCSR_PME_EN 0x04 /* control by PCISTICK */#define PWCFG_LEGACY_WOLSR 0x02 /* Legacy WOL_SR shadow */#define PWCFG_LEGACY_WOLEN 0x01 /* Legacy WOL_EN shadow *//* * Bits in WOLCFG */#define WOLCFG_PMEOVR 0x80 /* for legacy use, force PMEEN always */#define WOLCFG_SAM 0x20 /* accept multicast case reset, default=0 */#define WOLCFG_SAB 0x10 /* accept broadcast case reset, default=0 */#define WOLCFG_SMIIACC 0x08 /* ?? */#define WOLCFG_SGENWH 0x02#define WOLCFG_PHYINTEN 0x01 /* 0:PHYINT trigger enable, 1:use internal MII to report status change *//* * Bits in WOLSR1 */#define WOLSR_LINKOFF_INT 0x0800#define WOLSR_LINKON_INT 0x0400#define WOLSR_MAGIC_INT 0x0200#define WOLSR_UNICAST_INT 0x0100/* * Ethernet address filter type */#define PKT_TYPE_NONE 0x0000 /* Turn off receiver */#define PKT_TYPE_DIRECTED 0x0001 /* obselete, directed address is always accepted */#define PKT_TYPE_MULTICAST 0x0002#define PKT_TYPE_ALL_MULTICAST 0x0004#define PKT_TYPE_BROADCAST 0x0008#define PKT_TYPE_PROMISCUOUS 0x0020#define PKT_TYPE_LONG 0x2000 /* NOTE.... the definition of LONG is >2048 bytes in our chip */#define PKT_TYPE_RUNT 0x4000#define PKT_TYPE_ERROR 0x8000 /* Accept error packets, e.g. CRC error *//* * Loopback mode */#define MAC_LB_NONE 0x00#define MAC_LB_INTERNAL 0x01#define MAC_LB_EXTERNAL 0x02/* * Enabled mask value of irq */#if defined(_SIM)#define IMR_MASK_VALUE 0x0033FF0FUL /* initial value of IMR set IMR0 to 0x0F according to spec */#else#define IMR_MASK_VALUE 0x0013FB0FUL /* initial value of IMR ignore MIBFI,RACEI to reduce intr. frequency NOTE.... do not enable NoBuf int mask at driver driver when (1) NoBuf -> RxThreshold = SF (2) OK -> RxThreshold = original value */#endif/* * Revision id */#define REV_ID_VT3119_A0 0x00#define REV_ID_VT3119_A1 0x01#define REV_ID_VT3216_A0 0x10/* * Max time out delay time */#define W_MAX_TIMEOUT 0x0FFFU/* * MAC registers as a structure. Cannot be directly accessed this * way but generates offsets for readl/writel() calls */struct mac_regs { volatile u8 PAR[6]; /* 0x00 */ volatile u8 RCR; volatile u8 TCR; volatile u32 CR0Set; /* 0x08 */ volatile u32 CR0Clr; /* 0x0C */ volatile u8 MARCAM[8]; /* 0x10 */ volatile u32 DecBaseHi; /* 0x18 */ volatile u16 DbfBaseHi; /* 0x1C */ volatile u16 reserved_1E; volatile u16 ISRCTL; /* 0x20 */ volatile u8 TXESR; volatile u8 RXESR; volatile u32 ISR; /* 0x24 */ volatile u32 IMR; volatile u32 TDStatusPort; /* 0x2C */ volatile u16 TDCSRSet; /* 0x30 */ volatile u8 RDCSRSet; volatile u8 reserved_33; volatile u16 TDCSRClr; volatile u8 RDCSRClr; volatile u8 reserved_37; volatile u32 RDBaseLo; /* 0x38 */ volatile u16 RDIdx; /* 0x3C */ volatile u16 reserved_3E; volatile u32 TDBaseLo[4]; /* 0x40 */ volatile u16 RDCSize; /* 0x50 */ volatile u16 TDCSize; /* 0x52 */ volatile u16 TDIdx[4]; /* 0x54 */ volatile u16 tx_pause_timer; /* 0x5C */ volatile u16 RBRDU; /* 0x5E */ volatile u32 FIFOTest0; /* 0x60 */ volatile u32 FIFOTest1; /* 0x64 */ volatile u8 CAMADDR; /* 0x68 */ volatile u8 CAMCR; /* 0x69 */ volatile u8 GFTEST; /* 0x6A */ volatile u8 FTSTCMD; /* 0x6B */ volatile u8 MIICFG; /* 0x6C */ volatile u8 MIISR; volatile u8 PHYSR0; volatile u8 PHYSR1; volatile u8 MIICR; volatile u8 MIIADR; volatile u16 MIIDATA; volatile u16 SoftTimer0; /* 0x74 */ volatile u16 SoftTimer1; volatile u8 CFGA; /* 0x78 */ volatile u8 CFGB; volatile u8 CFGC; volatile u8 CFGD; volatile u16 DCFG; /* 0x7C */ volatile u16 MCFG; volatile u8 TBIST; /* 0x80 */ volatile u8 RBIST; volatile u8 PMCPORT; volatile u8 STICKHW; volatile u8 MIBCR; /* 0x84 */ volatile u8 reserved_85; volatile u8 rev_id; volatile u8 PORSTS; volatile u32 MIBData; /* 0x88 */ volatile u16 EEWrData; volatile u8 reserved_8E; volatile u8 BPMDWr; volatile u8 BPCMD; volatile u8 BPMDRd; volatile u8 EECHKSUM; /* 0x92 */ volatile u8 EECSR; volatile u16 EERdData; /* 0x94 */ volatile u8 EADDR; volatile u8 EMBCMD; volatile u8 JMPSR0; /* 0x98 */ volatile u8 JMPSR1; volatile u8 JMPSR2; volatile u8 JMPSR3; volatile u8 CHIPGSR; /* 0x9C */ volatile u8 TESTCFG; volatile u8 DEBUG; volatile u8 CHIPGCR; volatile u16 WOLCRSet; /* 0xA0 */ volatile u8 PWCFGSet; volatile u8 WOLCFGSet;⌨️ 快捷键说明
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